From 24851c9a3be2de826488edaa98218d92e928664f Mon Sep 17 00:00:00 2001
From: Mateusz Holenko <mholenko@antmicro.com>
Date: Thu, 13 Jun 2019 15:41:47 +0200
Subject: [PATCH] PhySettings: set missing databits parameter for
 S6QuarterRateDDRPHY

---
 litedram/phy/s6ddrphy.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/litedram/phy/s6ddrphy.py b/litedram/phy/s6ddrphy.py
index 67829c3..d92cacc 100644
--- a/litedram/phy/s6ddrphy.py
+++ b/litedram/phy/s6ddrphy.py
@@ -421,6 +421,7 @@ class S6QuarterRateDDRPHY(Module):
 
         self.settings = PhySettings(
             memtype="DDR3",
+            databits=databits,
             dfi_databits=2*databits,
             nranks=nranks,
             nphases=nphases,