From 67df00bcac14961a2e03dc4b70b80f2fc39a4908 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 29 Jun 2017 11:20:08 +0200 Subject: [PATCH] frontend/bist: use new reset_less attribute where possible --- litedram/frontend/bist.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/litedram/frontend/bist.py b/litedram/frontend/bist.py index 2f8aabb..cfc21f5 100644 --- a/litedram/frontend/bist.py +++ b/litedram/frontend/bist.py @@ -86,7 +86,7 @@ class _LiteDRAMBISTGenerator(Module): dma = LiteDRAMDMAWriter(dram_port) self.submodules += dma, gen - cmd_counter = Signal(dram_port.aw) + cmd_counter = Signal(dram_port.aw, reset_less=True) fsm = FSM(reset_state="IDLE") self.submodules += fsm @@ -209,7 +209,7 @@ class _LiteDRAMBISTChecker(Module, AutoCSR): self.submodules += dma, gen # address - cmd_counter = Signal(dram_port.aw) + cmd_counter = Signal(dram_port.aw, reset_less=True) cmd_fsm = FSM(reset_state="IDLE") self.submodules += cmd_fsm @@ -232,7 +232,7 @@ class _LiteDRAMBISTChecker(Module, AutoCSR): self.comb += dma.sink.address.eq(self.base + cmd_counter) # data - data_counter = Signal(dram_port.aw) + data_counter = Signal(dram_port.aw, reset_less=True) data_fsm = FSM(reset_state="IDLE") self.submodules += data_fsm