From 68e9a02a55caaeaa9cfcd73baabd21b7ca3ea185 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 29 Sep 2020 19:46:39 +0200 Subject: [PATCH] litedram/common: add cl/cwl values for DDR4 data rates from 1333MT/s to 2666MT/s. --- litedram/common.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/litedram/common.py b/litedram/common.py index a84a71a..79f3718 100644 --- a/litedram/common.py +++ b/litedram/common.py @@ -40,7 +40,12 @@ def get_cl_cw(memtype, tck): f_to_cl_cwl[1333e6] = (10, 7) f_to_cl_cwl[1600e6] = (11, 8) elif memtype == "DDR4": + f_to_cl_cwl[1333e6] = (9, 9) f_to_cl_cwl[1600e6] = (11, 9) + f_to_cl_cwl[1866e6] = (13, 10) + f_to_cl_cwl[2133e6] = (15, 11) + f_to_cl_cwl[2400e6] = (16, 12) + f_to_cl_cwl[2666e6] = (18, 14) else: raise ValueError for f, (cl, cwl) in f_to_cl_cwl.items():