diff --git a/litedram/modules.py b/litedram/modules.py
index 1f0fe75..9c0da61 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -136,6 +136,17 @@ class AS4C16M16(SDRAMModule):
     speedgrade_timings = {"default": _SpeedgradeTimings(tRP=18, tRCD=18, tWR=12, tRFC=60, tFAW=None, tRAS=None)}
 
 
+class AS4C32M16(SDRAMModule):
+    memtype = "SDR"
+    # geometry
+    nbanks = 4
+    nrows  = 8192
+    ncols  = 1024
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
+    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=18, tRCD=18, tWR=12, tRFC=60, tFAW=None, tRAS=None)}
+
+
 # DDR
 class MT46V32M16(SDRAMModule):
     memtype = "DDR"