From 69eaf844e85e49a5cf35881f19b0518aec79575f Mon Sep 17 00:00:00 2001
From:  <john@csquare.ca>
Date: Mon, 1 Oct 2018 19:35:20 -0400
Subject: [PATCH] Fix DDR2 and below compilation failure

---
 litedram/common.py | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/litedram/common.py b/litedram/common.py
index 4b9d39a..3104b53 100644
--- a/litedram/common.py
+++ b/litedram/common.py
@@ -24,7 +24,10 @@ class PhySettings:
         self.cl = cl
         self.read_latency = read_latency
         self.write_latency = write_latency
-        self.cwl = cwl
+        if cwl is None:
+            self.cwl = cl
+        else:
+            self.cwl = cwl
 
     # Optional DDR3 electrical settings
     def add_electrical_settings(self, rtt_nom, rtt_wr, ron):