diff --git a/litedram/init.py b/litedram/init.py
index 4adebca..fc6c289 100644
--- a/litedram/init.py
+++ b/litedram/init.py
@@ -701,24 +701,20 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
         r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
 
     # Define number of modules/delays/bitslips
+    r += "#define SDRAM_PHY_MODULES SDRAM_PHY_DATABITS/8\n"
     if phytype in ["USDDRPHY", "USPDDRPHY"]:
-        r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2\n"
         r += "#define SDRAM_PHY_DELAYS 512\n"
         r += "#define SDRAM_PHY_BITSLIPS 8\n"
     elif phytype in ["A7DDRPHY", "K7DDRPHY", "V7DDRPHY"]:
-        r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2\n"
         r += "#define SDRAM_PHY_DELAYS 32\n"
         r += "#define SDRAM_PHY_BITSLIPS 8\n"
     elif phytype in ["A7LPDDR4PHY", "K7LPDDR4PHY", "V7LPDDR4PHY"]:
-        r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2\n"
         r += "#define SDRAM_PHY_DELAYS 32\n"
         r += "#define SDRAM_PHY_BITSLIPS 16\n"
     elif phytype in ["ECP5DDRPHY"]:
-        r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/4\n"
         r += "#define SDRAM_PHY_DELAYS 8\n"
         r += "#define SDRAM_PHY_BITSLIPS 4\n"
     elif phytype in ["LPDDR4SIMPHY"]:
-        r += "#define SDRAM_PHY_MODULES 2\n"
         r += "#define SDRAM_PHY_DELAYS 1\n"
         r += "#define SDRAM_PHY_BITSLIPS 16\n"