From cbb699ce52bf16f72fff7c6cb6864d61cdc8e116 Mon Sep 17 00:00:00 2001 From: "Nathaniel R. Lewis" Date: Fri, 13 Nov 2020 13:17:01 -0800 Subject: [PATCH] modules: add AS4C128M16 DDR3L module --- litedram/modules.py | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/litedram/modules.py b/litedram/modules.py index ab0f413..4536eab 100644 --- a/litedram/modules.py +++ b/litedram/modules.py @@ -618,6 +618,18 @@ class P3R1GE4JGF(DDR2Module): class DDR3Module(SDRAMModule): memtype = "DDR3" class DDR3RegisteredModule(SDRAMRegisteredModule): memtype = "DDR3" +class AS4C128M16(DDR3Module): + # geometry + nbanks = 8 + nrows = 16384 + ncols = 1024 + # timings + technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 6), tZQCS=(64, 80)) + speedgrade_timings = { + "1600": _SpeedgradeTimings(tRP=13.75, tRCD=13.75, tWR=13.75, tRFC=(160, None), tFAW=(None, 40), tRAS=35), + } + speedgrade_timings["default"] = speedgrade_timings["1600"] + class MT41K64M16(DDR3Module): # geometry nbanks = 8