From 6c7a804986d8916bdc3d97ba2181c00787a5a91b Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Mon, 1 Oct 2018 18:49:10 -0700
Subject: [PATCH] Adding tCCD for DDR2 modules.

---
 litedram/modules.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/litedram/modules.py b/litedram/modules.py
index 62cef5d..8821ad5 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -194,6 +194,7 @@ class MT47H128M8(SDRAMModule):
     # speedgrade invariant timings
     tREFI = 64e6/8192
     tWTR = (None, 7.5)
+    tCCD  = (2, None)
     # speedgrade related timings
     tRP   = 15
     tRCD  = 15
@@ -210,6 +211,7 @@ class MT47H64M16(SDRAMModule):
     # speedgrade invariant timings
     tREFI = 64e6/8192
     tWTR = (None, 7.5)
+    tCCD  = (2, None)
     # speedgrade related timings
     tRP   = 15
     tRCD  = 15
@@ -227,6 +229,7 @@ class P3R1GE4JGF(SDRAMModule):
     # speedgrade invariant timings
     tREFI = 64e6/8192
     tWTR = (None, 7.5)
+    tCCD  = (2, None)
     # speedgrade related timings
     tRP   = 12.5
     tRCD  = 12.5