From 6dadc11b21a8253aa20305f1a54c1a2f1f4bbfd6 Mon Sep 17 00:00:00 2001
From: Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
Date: Fri, 25 Aug 2023 17:52:05 +0200
Subject: [PATCH] phy/gw2ddrphy: fix cl/cwl latencies

---
 litedram/phy/gw2ddrphy.py | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/litedram/phy/gw2ddrphy.py b/litedram/phy/gw2ddrphy.py
index edfda96..7215af2 100644
--- a/litedram/phy/gw2ddrphy.py
+++ b/litedram/phy/gw2ddrphy.py
@@ -174,8 +174,8 @@ class GW2DDRPHY(Module, AutoCSR):
             wrphase       = wrphase,
             cl            = cl,
             cwl           = cwl,
-            read_latency  = cl_sys_latency + 10,
-            write_latency = cwl_sys_latency,
+            read_latency  = cl_sys_latency + 9,
+            write_latency = cwl_sys_latency - 1,
             read_leveling = True,
             bitslips      = 4,
             delays        = 8,
@@ -433,7 +433,7 @@ class GW2DDRPHY(Module, AutoCSR):
                 )
 
         # Read Control Path ------------------------------------------------------------------------
-        rdtap = cl_sys_latency # CHECKME: Latency.
+        rdtap = cl_sys_latency - 1 # CHECKME: Latency.
 
         # Creates a delay line of read commands coming from the DFI interface. The taps are used to
         # control DQS read (internal read pulse of the DQSBUF) and the output of the delay is used
@@ -454,7 +454,7 @@ class GW2DDRPHY(Module, AutoCSR):
         self.comb += dqs_re.eq(rddata_en.taps[rdtap] | rddata_en.taps[rdtap + 1])
 
         # Write Control Path -----------------------------------------------------------------------
-        wrtap = cwl_sys_latency  # CHECKME: Latency.
+        wrtap = cwl_sys_latency - 1  # CHECKME: Latency.
 
         # Create a delay line of write commands coming from the DFI interface. This taps are used to
         # control DQ/DQS tristates and to select write data of the DRAM burst from the DFI interface.