From 6e10daed58bfa11acd09b43caa5eda45aa438bc2 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 25 Sep 2018 21:04:19 +0200 Subject: [PATCH] core/bankmachine/write to precharge: indicate that AL=0 --- litedram/core/bankmachine.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/core/bankmachine.py b/litedram/core/bankmachine.py index 1c77a34..9b22eb4 100644 --- a/litedram/core/bankmachine.py +++ b/litedram/core/bankmachine.py @@ -86,7 +86,7 @@ class BankMachine(Module): # Respect write-to-precharge specification write_latency = math.ceil(settings.phy.cwl / settings.phy.nphases) - precharge_time = write_latency + settings.timing.tWR - 1 + settings.timing.tCCD + precharge_time = write_latency + settings.timing.tWR - 1 + settings.timing.tCCD # AL=0 precharge_timer = WaitTimer(precharge_time) self.submodules += precharge_timer self.comb += precharge_timer.wait.eq(~(cmd.valid & cmd.ready & cmd.is_write))