From 6e8d37c8735158a11000f2e5309b91cfb803a0df Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 8 Oct 2020 16:57:12 +0200
Subject: [PATCH] phy/s7ddrphy: replace dm/dq delays with BitSlip.

---
 litedram/phy/s7ddrphy.py | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/litedram/phy/s7ddrphy.py b/litedram/phy/s7ddrphy.py
index 442c81c..88b143e 100644
--- a/litedram/phy/s7ddrphy.py
+++ b/litedram/phy/s7ddrphy.py
@@ -98,7 +98,7 @@ class S7DDRPHY(Module, AutoCSR):
             cl            = cl,
             cwl           = cwl,
             read_latency  = cl_sys_latency + 6,
-            write_latency = cwl_sys_latency - 1,
+            write_latency = cwl_sys_latency - 2,
             cmd_latency   = cmd_latency,
             cmd_delay     = cmd_delay,
         )
@@ -264,9 +264,10 @@ class S7DDRPHY(Module, AutoCSR):
         # DM ---------------------------------------------------------------------------------------
         for i in range(databits//8):
             dm_o_nodelay = Signal()
-            _dm = Cat(*[dfi.phases[n//2].wrdata_mask[n%2*databits//8+i] for n in range(8)])
-            dm = Signal(8)
-            self.sync += dm.eq(_dm)
+            dm_o_bitslip =  BitSlip(8,
+                i      = Cat(*[dfi.phases[n//2].wrdata_mask[n%2*databits//8+i] for n in range(8)]),
+                cycles = 1)
+            self.submodules += dm_o_bitslip
             self.specials += Instance("OSERDESE2",
                 p_SERDES_MODE    = "MASTER",
                 p_DATA_WIDTH     = 2*nphases,
@@ -276,7 +277,7 @@ class S7DDRPHY(Module, AutoCSR):
                 i_RST    = ResetSignal() | self._rst.storage,
                 i_CLK    = ClockSignal(ddr_clk),
                 i_CLKDIV = ClockSignal(),
-                **{f"i_D{n+1}": dm[n] for n in range(8)},
+                **{f"i_D{n+1}": dm_o_bitslip.o[n] for n in range(8)},
                 i_OCE    = 1,
                 o_OQ     = dm_o_nodelay if with_odelay else pads.dm[i],
             )
@@ -311,9 +312,10 @@ class S7DDRPHY(Module, AutoCSR):
             dq_i_delayed = Signal()
             dq_t         = Signal()
             dq_i_data    = Signal(8)
-            _dq = Cat(*[dfi.phases[n//2].wrdata[n%2*databits+i] for n in range(8)])
-            dq = Signal(8)
-            self.sync += dq.eq(_dq)
+            dq_o_bitslip =  BitSlip(8,
+                i      = Cat(*[dfi.phases[n//2].wrdata[n%2*databits+i] for n in range(8)]),
+                cycles = 1)
+            self.submodules += dq_o_bitslip
             self.specials += Instance("OSERDESE2",
                 p_SERDES_MODE    = "MASTER",
                 p_DATA_WIDTH     = 2*nphases,
@@ -323,7 +325,7 @@ class S7DDRPHY(Module, AutoCSR):
                 i_RST    = ResetSignal() | self._rst.storage,
                 i_CLK    = ClockSignal(ddr_clk),
                 i_CLKDIV = ClockSignal(),
-                **{f"i_D{n+1}": dq[n] for n in range(8)},
+                **{f"i_D{n+1}": dq_o_bitslip.o[n] for n in range(8)},
                 i_TCE    = 1,
                 i_T1     = ~dq_oe_delay.output,
                 o_TQ     = dq_t,