From 6f10314d436d05fe805ac9c71ee566612a85f07f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 23 May 2016 17:37:30 +0200 Subject: [PATCH] frontend/bist: remove cd parameter (already available with dram_port.cd) --- litedram/frontend/bist.py | 4 +++- test/bist_async_tb.py | 4 ++-- test/bist_tb.py | 4 ++-- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/litedram/frontend/bist.py b/litedram/frontend/bist.py index 56a014c..0d5deb0 100644 --- a/litedram/frontend/bist.py +++ b/litedram/frontend/bist.py @@ -68,7 +68,7 @@ class _LiteDRAMBISTGenerator(Module): class LiteDRAMBISTGenerator(Module, AutoCSR): - def __init__(self, dram_port, cd="sys"): + def __init__(self, dram_port): self.reset = CSR() self.shoot = CSR() self.done = CSRStatus() @@ -77,6 +77,8 @@ class LiteDRAMBISTGenerator(Module, AutoCSR): # # # + cd = dram_port.cd + generator = _LiteDRAMBISTGenerator(dram_port) self.submodules += ClockDomainsRenamer(cd)(generator) diff --git a/test/bist_async_tb.py b/test/bist_async_tb.py index 78c3c23..afdb03f 100644 --- a/test/bist_async_tb.py +++ b/test/bist_async_tb.py @@ -51,8 +51,8 @@ class TB(Module): self.controller.nrowbits) self.write_port = self.crossbar.get_port(cd="write") self.read_port = self.crossbar.get_port(cd="read") - self.submodules.generator = LiteDRAMBISTGenerator(self.write_port, cd="write") - self.submodules.checker = LiteDRAMBISTChecker(self.read_port, cd="read") + self.submodules.generator = LiteDRAMBISTGenerator(self.write_port) + self.submodules.checker = LiteDRAMBISTChecker(self.read_port) def main_generator(dut): diff --git a/test/bist_tb.py b/test/bist_tb.py index ea659ed..ab23f92 100644 --- a/test/bist_tb.py +++ b/test/bist_tb.py @@ -10,8 +10,8 @@ from test.common import DRAMMemory class TB(Module): def __init__(self): - self.write_port = LiteDRAMPort(aw=32, dw=32, cd="sys") - self.read_port = LiteDRAMPort(aw=32, dw=32, cd="sys") + self.write_port = LiteDRAMPort(aw=32, dw=32) + self.read_port = LiteDRAMPort(aw=32, dw=32) self.submodules.generator = LiteDRAMBISTGenerator(self.write_port) self.submodules.checker = LiteDRAMBISTChecker(self.read_port)