frontend/bist: remove cd parameter (already available with dram_port.cd)
This commit is contained in:
parent
b258c9a913
commit
6f10314d43
|
@ -68,7 +68,7 @@ class _LiteDRAMBISTGenerator(Module):
|
||||||
|
|
||||||
|
|
||||||
class LiteDRAMBISTGenerator(Module, AutoCSR):
|
class LiteDRAMBISTGenerator(Module, AutoCSR):
|
||||||
def __init__(self, dram_port, cd="sys"):
|
def __init__(self, dram_port):
|
||||||
self.reset = CSR()
|
self.reset = CSR()
|
||||||
self.shoot = CSR()
|
self.shoot = CSR()
|
||||||
self.done = CSRStatus()
|
self.done = CSRStatus()
|
||||||
|
@ -77,6 +77,8 @@ class LiteDRAMBISTGenerator(Module, AutoCSR):
|
||||||
|
|
||||||
# # #
|
# # #
|
||||||
|
|
||||||
|
cd = dram_port.cd
|
||||||
|
|
||||||
generator = _LiteDRAMBISTGenerator(dram_port)
|
generator = _LiteDRAMBISTGenerator(dram_port)
|
||||||
self.submodules += ClockDomainsRenamer(cd)(generator)
|
self.submodules += ClockDomainsRenamer(cd)(generator)
|
||||||
|
|
||||||
|
|
|
@ -51,8 +51,8 @@ class TB(Module):
|
||||||
self.controller.nrowbits)
|
self.controller.nrowbits)
|
||||||
self.write_port = self.crossbar.get_port(cd="write")
|
self.write_port = self.crossbar.get_port(cd="write")
|
||||||
self.read_port = self.crossbar.get_port(cd="read")
|
self.read_port = self.crossbar.get_port(cd="read")
|
||||||
self.submodules.generator = LiteDRAMBISTGenerator(self.write_port, cd="write")
|
self.submodules.generator = LiteDRAMBISTGenerator(self.write_port)
|
||||||
self.submodules.checker = LiteDRAMBISTChecker(self.read_port, cd="read")
|
self.submodules.checker = LiteDRAMBISTChecker(self.read_port)
|
||||||
|
|
||||||
|
|
||||||
def main_generator(dut):
|
def main_generator(dut):
|
||||||
|
|
|
@ -10,8 +10,8 @@ from test.common import DRAMMemory
|
||||||
|
|
||||||
class TB(Module):
|
class TB(Module):
|
||||||
def __init__(self):
|
def __init__(self):
|
||||||
self.write_port = LiteDRAMPort(aw=32, dw=32, cd="sys")
|
self.write_port = LiteDRAMPort(aw=32, dw=32)
|
||||||
self.read_port = LiteDRAMPort(aw=32, dw=32, cd="sys")
|
self.read_port = LiteDRAMPort(aw=32, dw=32)
|
||||||
self.submodules.generator = LiteDRAMBISTGenerator(self.write_port)
|
self.submodules.generator = LiteDRAMBISTGenerator(self.write_port)
|
||||||
self.submodules.checker = LiteDRAMBISTChecker(self.read_port)
|
self.submodules.checker = LiteDRAMBISTChecker(self.read_port)
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue