From 6f323f6a7aa032c8342b5931f4a562d2e28969e9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 14 Sep 2021 16:32:31 +0200 Subject: [PATCH] phy/s7ddrphy: Add +1 to CL in MR register to increase sys_clk_freq range. Allow successful DDR3 calibration at lower sys_clk_freq (tested down to 50MHz). --- litedram/phy/s7ddrphy.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/litedram/phy/s7ddrphy.py b/litedram/phy/s7ddrphy.py index 28db922..ba4d113 100644 --- a/litedram/phy/s7ddrphy.py +++ b/litedram/phy/s7ddrphy.py @@ -117,6 +117,10 @@ class S7DDRPHY(Module, AutoCSR): wdly_dq_bitslip = cdc(self._wdly_dq_bitslip.re) # PHY settings ----------------------------------------------------------------------------- + if not with_odelay: + # Write leveling is not possible on Artix7 due to the lack of ODELAYE2, adding +1 to cl + # in MR register increases sys_clk_freq range. + cl += 1 self.settings = PhySettings( phytype = phytype, memtype = memtype,