From 6fa891d5d64ba9495802940ca3273c21e5e7cc48 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 12 Nov 2018 18:02:54 +0100 Subject: [PATCH] frontend/axi: fix write response for bursts --- litedram/frontend/axi.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/litedram/frontend/axi.py b/litedram/frontend/axi.py index 1bcfffd..0a1ccaf 100644 --- a/litedram/frontend/axi.py +++ b/litedram/frontend/axi.py @@ -97,6 +97,7 @@ class LiteDRAMAXIBurst2Beat(Module): self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", ax_beat.valid.eq(ax_burst.valid), + ax_beat.first.eq(1), ax_beat.last.eq(ax_burst.len == 0), ax_beat.addr.eq(ax_burst.addr), ax_beat.id.eq(ax_burst.id), @@ -114,6 +115,7 @@ class LiteDRAMAXIBurst2Beat(Module): self.sync += wrap_offset.eq((ax_burst.len - 1)*size) fsm.act("BURST2BEAT", ax_beat.valid.eq(1), + ax_beat.first.eq(0), ax_beat.last.eq(count == ax_burst.len), If((ax_burst.burst == burst_types["incr"]) | (ax_burst.burst == burst_types["wrap"]), @@ -163,7 +165,7 @@ class LiteDRAMAXI2NativeW(Module): resp_buffer = stream.SyncFIFO([("id", axi.id_width), ("resp", 2)], buffer_depth) self.submodules += id_buffer, resp_buffer self.comb += [ - id_buffer.sink.valid.eq(aw.valid & aw.ready), + id_buffer.sink.valid.eq(aw.valid & aw.first & aw.ready), id_buffer.sink.id.eq(aw.id), If(w_buffer.source.valid & w_buffer.source.last &