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bench/genesys2: expose uart parameter.

This commit is contained in:
Florent Kermarrec 2020-09-17 08:22:17 +02:00
parent 8525a27762
commit 6fc6174c38
1 changed files with 7 additions and 7 deletions
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14
bench/genesys2.py
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@ -59,7 +59,7 @@ class _CRG(Module, AutoCSR):
# Bench SoC ----------------------------------------------------------------------------------------
class BenchSoC(SoCCore):
def __init__(self, uart_name="serial", sys_clk_freq=int(175e6)):
def __init__(self, uart="crossover", sys_clk_freq=int(175e6)):
platform = genesys2.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -67,7 +67,7 @@ class BenchSoC(SoCCore):
integrated_rom_size = 0x8000,
integrated_rom_mode = "rw",
csr_data_width = 32,
uart_name = uart_name)
uart_name = uart)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
@ -77,8 +77,7 @@ class BenchSoC(SoCCore):
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq,
cmd_latency = 0)
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
@ -87,7 +86,7 @@ class BenchSoC(SoCCore):
)
# UARTBone ---------------------------------------------------------------------------------
if uart_name != "serial":
if uart != "serial":
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
# Etherbone --------------------------------------------------------------------------------
@ -109,6 +108,7 @@ class BenchSoC(SoCCore):
def main():
parser = argparse.ArgumentParser(description="LiteDRAM Bench on Genesys2")
parser.add_argument("--uart", default="crossover", help="Selected UART: crossover (default) or serial")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--load-bios", action="store_true", help="Load BIOS")
@ -116,7 +116,7 @@ def main():
parser.add_argument("--test", action="store_true", help="Run Full Bench")
args = parser.parse_args()
soc = BenchSoC()
soc = BenchSoC(uart=args.uart)
builder = Builder(soc, csr_csv="csr.csv")
builder.build(run=args.build)
@ -124,7 +124,7 @@ def main():
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
if args.load_bios is not None:
if args.load_bios:
from common import s7_load_bios
s7_load_bios("build/genesys2/software/bios/bios.bin")