diff --git a/litedram/phy/a7ddrphy.py b/litedram/phy/a7ddrphy.py
index 29626c9..8b083c4 100644
--- a/litedram/phy/a7ddrphy.py
+++ b/litedram/phy/a7ddrphy.py
@@ -41,26 +41,27 @@ class A7DDRPHY(Module, AutoCSR):
         # # #
 
         # Clock
-        sd_clk_se = Signal()
-        self.specials += [
-            Instance("OSERDESE2",
-                p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
-                p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF",
-                p_SERDES_MODE="MASTER",
+        for i in range(len(pads.clk_p)):
+            sd_clk_se = Signal()
+            self.specials += [
+                Instance("OSERDESE2",
+                    p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
+                    p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF",
+                    p_SERDES_MODE="MASTER",
 
-                o_OQ=sd_clk_se,
-                i_OCE=1,
-                i_RST=ResetSignal(),
-                i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
-                i_D1=0, i_D2=1, i_D3=0, i_D4=1,
-                i_D5=0, i_D6=1, i_D7=0, i_D8=1
-            ),
-            Instance("OBUFDS",
-                i_I=sd_clk_se,
-                o_O=pads.clk_p,
-                o_OB=pads.clk_n
-            )
-        ]
+                    o_OQ=sd_clk_se,
+                    i_OCE=1,
+                    i_RST=ResetSignal(),
+                    i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
+                    i_D1=0, i_D2=1, i_D3=0, i_D4=1,
+                    i_D5=0, i_D6=1, i_D7=0, i_D8=1
+                ),
+                Instance("OBUFDS",
+                    i_I=sd_clk_se,
+                    o_O=pads.clk_p[i],
+                    o_OB=pads.clk_n[i]
+                )
+            ]
 
         # Addresses and commands
         for i in range(addressbits):
diff --git a/setup.py b/setup.py
index 63410a9..406801e 100755
--- a/setup.py
+++ b/setup.py
@@ -11,25 +11,25 @@ if sys.version_info[:3] < (3, 3):
 
 setup(
     name="litedram",
-	version="0.1",
+    version="0.1",
     description="Small footprint and configurable dram core",
-	long_description=open("README").read(),
-	author="Florent Kermarrec",
-	author_email="florent@enjoy-digital.fr",
-	url="http://enjoy-digital.fr",
+    long_description=open("README").read(),
+    author="Florent Kermarrec",
+    author_email="florent@enjoy-digital.fr",
+    url="http://enjoy-digital.fr",
     download_url="https://github.com/enjoy-digital/litedram",
     test_suite="test",
     license="BSD",
     platforms=["Any"],
     keywords="HDL ASIC FPGA hardware design",
-	classifiers=[
-		"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
-		"Environment :: Console",
-		"Development Status :: Alpha",
-		"Intended Audience :: Developers",
+    classifiers=[
+        "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
+        "Environment :: Console",
+        "Development Status :: Alpha",
+        "Intended Audience :: Developers",
         "License :: OSI Approved :: BSD License",
-		"Operating System :: OS Independent",
-		"Programming Language :: Python",
+        "Operating System :: OS Independent",
+        "Programming Language :: Python",
     ],
     packages=find_packages(),
     include_package_data=True,
diff --git a/test/test_bist_async.py b/test/test_bist_async.py
index 3df3f53..909ce77 100755
--- a/test/test_bist_async.py
+++ b/test/test_bist_async.py
@@ -75,7 +75,7 @@ def main_generator(dut):
     checker = BISTDriver(dut.checker)
 
     for i in range(16):
-    	yield
+        yield
 
     # write
     yield from generator.reset()