From 7356d3b15d9d80eace033fdd1deceee419e5cf71 Mon Sep 17 00:00:00 2001 From: Gabriel Somlo Date: Thu, 24 Oct 2019 11:31:56 -0400 Subject: [PATCH] frontend/wishbone: add base_address param. to LiteDRAMWishbone2Native --- litedram/frontend/wishbone.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/litedram/frontend/wishbone.py b/litedram/frontend/wishbone.py index 251d28e..28431a9 100644 --- a/litedram/frontend/wishbone.py +++ b/litedram/frontend/wishbone.py @@ -7,11 +7,13 @@ from migen import * class LiteDRAMWishbone2Native(Module): - def __init__(self, wishbone, port): + def __init__(self, wishbone, port, base_address=0x00000000): assert len(wishbone.dat_w) == len(port.wdata.data) # # # + adr_offset = base_address >> log2_int(port.data_width//8) + # Control self.submodules.fsm = fsm = FSM(reset_state="CMD") fsm.act("CMD", @@ -43,7 +45,7 @@ class LiteDRAMWishbone2Native(Module): # Datapath self.comb += [ # cmd - port.cmd.addr.eq(wishbone.adr), + port.cmd.addr.eq(wishbone.adr - adr_offset), # write port.wdata.we.eq(wishbone.sel), port.wdata.data.eq(wishbone.dat_w),