From 73d614ef2737d415b1a7e2320bc3b7664ddf216a Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 30 Nov 2019 11:06:41 +0100
Subject: [PATCH] frontend/wishbone: remove LiteDRAMWishbone2AXI (can be
 replaced with LiteX's Wishbone2AXILite)

---
 litedram/frontend/wishbone.py | 58 -----------------------------------
 1 file changed, 58 deletions(-)

diff --git a/litedram/frontend/wishbone.py b/litedram/frontend/wishbone.py
index 08cbd8d..bdd39f2 100644
--- a/litedram/frontend/wishbone.py
+++ b/litedram/frontend/wishbone.py
@@ -53,61 +53,3 @@ class LiteDRAMWishbone2Native(Module):
             # Read
             wishbone.dat_r.eq(port.rdata.data),
         ]
-
-
-# LiteDRAMWishbone2AXI -----------------------------------------------------------------------------
-
-class LiteDRAMWishbone2AXI(Module):
-    def __init__(self, wishbone, port):
-        assert len(wishbone.dat_w) == len(port.w.data)
-
-        # # #
-
-        ashift = log2_int(port.data_width//8)
-
-        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
-        fsm.act("IDLE",
-            If(wishbone.cyc & wishbone.stb,
-                If(wishbone.we,
-                    NextValue(port.aw.valid, 1),
-                    NextValue(port.w.valid, 1),
-                    NextState("WRITE")
-                ).Else(
-                    NextValue(port.ar.valid, 1),
-                    NextState("READ")
-                )
-            )
-        )
-        fsm.act("WRITE",
-            port.aw.size.eq(ashift),
-            port.aw.addr[ashift:].eq(wishbone.adr),
-            port.w.last.eq(1),
-            port.w.data.eq(wishbone.dat_w),
-            port.w.strb.eq(wishbone.sel),
-            If(port.aw.ready,
-                NextValue(port.aw.valid, 0)
-            ),
-            If(port.w.ready,
-                NextValue(port.w.valid, 0)
-            ),
-            If(port.b.valid,
-                port.b.ready.eq(1),
-                wishbone.ack.eq(1),
-                wishbone.err.eq(port.b.resp != 0b00),
-                NextState("IDLE")
-            )
-        )
-        fsm.act("READ",
-            port.ar.size.eq(ashift),
-            port.ar.addr[ashift:].eq(wishbone.adr),
-            If(port.ar.ready,
-                NextValue(port.ar.valid, 0)
-            ),
-            If(port.r.valid,
-                port.r.ready.eq(1),
-                wishbone.dat_r.eq(port.r.data),
-                wishbone.ack.eq(1),
-                wishbone.err.eq(port.r.resp != 0b00),
-                NextState("IDLE")
-            )
-        )