From 74f72f91a03156cfa23b7615dabd81c858d0b933 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 26 Jan 2020 21:14:20 +0100 Subject: [PATCH] phy/usddrphy: reorder primitives parameters/signals --- litedram/phy/usddrphy.py | 125 ++++++++++++++++++++------------------- 1 file changed, 63 insertions(+), 62 deletions(-) diff --git a/litedram/phy/usddrphy.py b/litedram/phy/usddrphy.py index 6a27859..0ade803 100644 --- a/litedram/phy/usddrphy.py +++ b/litedram/phy/usddrphy.py @@ -98,13 +98,14 @@ class USDDRPHY(Module, AutoCSR): Instance("OSERDESE3", p_DATA_WIDTH = 8, p_INIT = 0, + p_IS_RST_INVERTED = 0, p_IS_CLK_INVERTED = 0, p_IS_CLKDIV_INVERTED = 0, - p_IS_RST_INVERTED = 0, - o_OQ = clk_o_nodelay, - i_RST = ResetSignal(), - i_CLK = ClockSignal("sys4x"), i_CLKDIV=ClockSignal(), - i_D = 0b10101010 + i_RST = ResetSignal(), + i_CLK = ClockSignal("sys4x"), + i_CLKDIV = ClockSignal(), + i_D = 0b10101010, + o_OQ = clk_o_nodelay, ), Instance("ODELAYE3", p_CASCADE = "NONE", @@ -113,18 +114,18 @@ class USDDRPHY(Module, AutoCSR): p_DELAY_FORMAT = "TIME", p_DELAY_TYPE = "VARIABLE", p_DELAY_VALUE = 0, - i_CLK = ClockSignal(), - i_INC = 1, - i_EN_VTC = self._en_vtc.storage, i_RST = self._cdly_rst.re, + i_CLK = ClockSignal(), + i_EN_VTC = self._en_vtc.storage, i_CE = self._cdly_inc.re, + i_INC = 1, i_ODATAIN = clk_o_nodelay, - o_DATAOUT = clk_o_delayed + o_DATAOUT = clk_o_delayed, ), Instance("OBUFDS", i_I = clk_o_delayed, o_O = pads.clk_p, - o_OB = pads.clk_n + o_OB = pads.clk_n, ) ] @@ -135,17 +136,17 @@ class USDDRPHY(Module, AutoCSR): Instance("OSERDESE3", p_DATA_WIDTH = 8, p_INIT = 0, + p_IS_RST_INVERTED = 0, p_IS_CLK_INVERTED = 0, p_IS_CLKDIV_INVERTED = 0, - p_IS_RST_INVERTED = 0, - o_OQ = a_o_nodelay, i_RST = ResetSignal(), i_CLK = ClockSignal("sys4x"), i_CLKDIV = ClockSignal(), i_D = Cat(dfi.phases[0].address[i], dfi.phases[0].address[i], dfi.phases[1].address[i], dfi.phases[1].address[i], dfi.phases[2].address[i], dfi.phases[2].address[i], - dfi.phases[3].address[i], dfi.phases[3].address[i]) + dfi.phases[3].address[i], dfi.phases[3].address[i]), + o_OQ = a_o_nodelay, ), Instance("ODELAYE3", p_CASCADE = "NONE", @@ -154,13 +155,13 @@ class USDDRPHY(Module, AutoCSR): p_DELAY_FORMAT = "TIME", p_DELAY_TYPE = "VARIABLE", p_DELAY_VALUE = 0, - i_CLK = ClockSignal(), - i_INC = 1, - i_EN_VTC = self._en_vtc.storage, i_RST = self._cdly_rst.re, + i_CLK = ClockSignal(), + i_EN_VTC = self._en_vtc.storage, i_CE = self._cdly_inc.re, + i_INC = 1, i_ODATAIN = a_o_nodelay, - o_DATAOUT = pads.a[i] + o_DATAOUT = pads.a[i], ) ] @@ -176,10 +177,9 @@ class USDDRPHY(Module, AutoCSR): Instance("OSERDESE3", p_DATA_WIDTH = 8, p_INIT = 0, + p_IS_RST_INVERTED = 0, p_IS_CLK_INVERTED = 0, p_IS_CLKDIV_INVERTED = 0, - p_IS_RST_INVERTED = 0, - o_OQ = ba_o_nodelay, i_RST = ResetSignal(), i_CLK = ClockSignal("sys4x"), i_CLKDIV = ClockSignal(), @@ -187,7 +187,8 @@ class USDDRPHY(Module, AutoCSR): dfi.phases[0].bank[i], dfi.phases[0].bank[i], dfi.phases[1].bank[i], dfi.phases[1].bank[i], dfi.phases[2].bank[i], dfi.phases[2].bank[i], - dfi.phases[3].bank[i], dfi.phases[3].bank[i]) + dfi.phases[3].bank[i], dfi.phases[3].bank[i]), + o_OQ = ba_o_nodelay, ), Instance("ODELAYE3", p_CASCADE = "NONE", @@ -196,13 +197,13 @@ class USDDRPHY(Module, AutoCSR): p_DELAY_FORMAT = "TIME", p_DELAY_TYPE = "VARIABLE", p_DELAY_VALUE = 0, - i_CLK = ClockSignal(), - i_INC = 1, - i_EN_VTC = self._en_vtc.storage, i_RST = self._cdly_rst.re, + i_CLK = ClockSignal(), + i_EN_VTC = self._en_vtc.storage, i_CE = self._cdly_inc.re, + i_INC = 1, i_ODATAIN = ba_o_nodelay, - o_DATAOUT = pads_ba[i] + o_DATAOUT = pads_ba[i], ) ] @@ -219,10 +220,9 @@ class USDDRPHY(Module, AutoCSR): Instance("OSERDESE3", p_DATA_WIDTH = 8, p_INIT = 0, + p_IS_RST_INVERTED = 0, p_IS_CLK_INVERTED = 0, p_IS_CLKDIV_INVERTED = 0, - p_IS_RST_INVERTED = 0, - o_OQ = x_o_nodelay, i_RST = ResetSignal(), i_CLK = ClockSignal("sys4x"), i_CLKDIV = ClockSignal(), @@ -230,7 +230,8 @@ class USDDRPHY(Module, AutoCSR): getattr(dfi.phases[0], name), getattr(dfi.phases[0], name), getattr(dfi.phases[1], name), getattr(dfi.phases[1], name), getattr(dfi.phases[2], name), getattr(dfi.phases[2], name), - getattr(dfi.phases[3], name), getattr(dfi.phases[3], name)) + getattr(dfi.phases[3], name), getattr(dfi.phases[3], name)), + o_OQ = x_o_nodelay, ), Instance("ODELAYE3", p_CASCADE = "NONE", @@ -239,13 +240,13 @@ class USDDRPHY(Module, AutoCSR): p_DELAY_FORMAT = "TIME", p_DELAY_TYPE = "VARIABLE", p_DELAY_VALUE = 0, - i_CLK = ClockSignal(), - i_INC = 1, - i_EN_VTC = self._en_vtc.storage, i_RST = self._cdly_rst.re, + i_CLK = ClockSignal(), + i_EN_VTC = self._en_vtc.storage, i_CE = self._cdly_inc.re, + i_INC = 1, i_ODATAIN = x_o_nodelay, - o_DATAOUT = getattr(pads, name) + o_DATAOUT = getattr(pads, name), ) ] @@ -267,10 +268,9 @@ class USDDRPHY(Module, AutoCSR): Instance("OSERDESE3", p_DATA_WIDTH = 8, p_INIT = 0, + p_IS_RST_INVERTED = 0, p_IS_CLK_INVERTED = 0, p_IS_CLKDIV_INVERTED = 0, - p_IS_RST_INVERTED = 0, - o_OQ = dm_o_nodelay, i_RST = ResetSignal(), i_CLK = ClockSignal("sys4x"), i_CLKDIV = ClockSignal(), @@ -278,7 +278,8 @@ class USDDRPHY(Module, AutoCSR): dfi.phases[0].wrdata_mask[i], dfi.phases[0].wrdata_mask[databits//8+i], dfi.phases[1].wrdata_mask[i], dfi.phases[1].wrdata_mask[databits//8+i], dfi.phases[2].wrdata_mask[i], dfi.phases[2].wrdata_mask[databits//8+i], - dfi.phases[3].wrdata_mask[i], dfi.phases[3].wrdata_mask[databits//8+i]) + dfi.phases[3].wrdata_mask[i], dfi.phases[3].wrdata_mask[databits//8+i]), + o_OQ = dm_o_nodelay, ), Instance("ODELAYE3", p_CASCADE = "NONE", @@ -289,13 +290,13 @@ class USDDRPHY(Module, AutoCSR): p_DELAY_FORMAT = "TIME", p_DELAY_TYPE = "VARIABLE", p_DELAY_VALUE = 0, - i_CLK = ClockSignal(), - i_INC = 1, - i_EN_VTC = self._en_vtc.storage, i_RST = self._dly_sel.storage[i] & self._wdly_dq_rst.re, + i_EN_VTC = self._en_vtc.storage, + i_CLK = ClockSignal(), i_CE = self._dly_sel.storage[i] & self._wdly_dq_inc.re, + i_INC = 1, i_ODATAIN = dm_o_nodelay, - o_DATAOUT = pads.dm[i] + o_DATAOUT = pads.dm[i], ) ] @@ -318,11 +319,9 @@ class USDDRPHY(Module, AutoCSR): Instance("OSERDESE3", p_DATA_WIDTH = 8, p_INIT = 0, + p_IS_RST_INVERTED = 0, p_IS_CLK_INVERTED = 0, p_IS_CLKDIV_INVERTED = 0, - p_IS_RST_INVERTED = 0, - o_OQ = dqs_nodelay, - o_T_OUT = dqs_t, i_RST = ResetSignal(), i_CLK = ClockSignal("sys4x"), i_CLKDIV = ClockSignal(), @@ -332,6 +331,8 @@ class USDDRPHY(Module, AutoCSR): dqs_serdes_pattern[2], dqs_serdes_pattern[3], dqs_serdes_pattern[4], dqs_serdes_pattern[5], dqs_serdes_pattern[6], dqs_serdes_pattern[7]), + o_OQ = dqs_nodelay, + o_T_OUT = dqs_t, ), Instance("ODELAYE3", @@ -343,20 +344,20 @@ class USDDRPHY(Module, AutoCSR): p_DELAY_FORMAT = "TIME", p_DELAY_TYPE = "VARIABLE", p_DELAY_VALUE = int(tck*1e12/4), - i_CLK = ClockSignal(), - i_INC = 1, - i_EN_VTC = self._en_vtc.storage, i_RST = self._dly_sel.storage[i] & self._wdly_dqs_rst.re, + i_CLK = ClockSignal(), + i_EN_VTC = self._en_vtc.storage, i_CE = self._dly_sel.storage[i] & self._wdly_dqs_inc.re, + i_INC = 1, o_CNTVALUEOUT = Signal(9) if i != 0 else dqs_taps, i_ODATAIN = dqs_nodelay, - o_DATAOUT = dqs_delayed + o_DATAOUT = dqs_delayed, ), Instance("IOBUFDSE3", i_I = dqs_delayed, i_T = dqs_t, io_IO = pads.dqs_p[i], - io_IOB = pads.dqs_n[i] + io_IOB = pads.dqs_n[i], ) ] @@ -382,11 +383,9 @@ class USDDRPHY(Module, AutoCSR): Instance("OSERDESE3", p_DATA_WIDTH = 8, p_INIT = 0, + p_IS_RST_INVERTED = 0, p_IS_CLK_INVERTED = 0, p_IS_CLKDIV_INVERTED = 0, - p_IS_RST_INVERTED = 0, - o_OQ = dq_o_nodelay, - o_T_OUT = dq_t, i_RST = ResetSignal(), i_CLK = ClockSignal("sys4x"), i_CLKDIV = ClockSignal(), @@ -395,19 +394,21 @@ class USDDRPHY(Module, AutoCSR): dfi.phases[1].wrdata[i], dfi.phases[1].wrdata[databits+i], dfi.phases[2].wrdata[i], dfi.phases[2].wrdata[databits+i], dfi.phases[3].wrdata[i], dfi.phases[3].wrdata[databits+i]), - i_T = ~oe_dq + i_T = ~oe_dq, + o_OQ = dq_o_nodelay, + o_T_OUT = dq_t, ), Instance("ISERDESE3", p_IS_CLK_INVERTED = 0, p_IS_CLK_B_INVERTED = 1, p_DATA_WIDTH = 8, - i_D = dq_i_delayed, i_RST = ResetSignal(), - i_FIFO_RD_EN = 0, i_CLK = ClockSignal("sys4x"), i_CLK_B = ClockSignal("sys4x"), # locally inverted i_CLKDIV = ClockSignal(), - o_Q = dq_bitslip.i + i_D = dq_i_delayed, + i_FIFO_RD_EN = 0, + o_Q = dq_bitslip.i, ), Instance("ODELAYE3", p_CASCADE = "NONE", @@ -418,13 +419,13 @@ class USDDRPHY(Module, AutoCSR): p_DELAY_FORMAT = "TIME", p_DELAY_TYPE = "VARIABLE", p_DELAY_VALUE = 0, - i_CLK = ClockSignal(), - i_INC = 1, - i_EN_VTC = self._en_vtc.storage, i_RST = self._dly_sel.storage[i//8] & self._wdly_dq_rst.re, + i_CLK = ClockSignal(), + i_EN_VTC = self._en_vtc.storage, i_CE = self._dly_sel.storage[i//8] & self._wdly_dq_inc.re, + i_INC = 1, i_ODATAIN = dq_o_nodelay, - o_DATAOUT = dq_o_delayed + o_DATAOUT = dq_o_delayed, ), Instance("IDELAYE3", p_CASCADE = "NONE", @@ -436,19 +437,19 @@ class USDDRPHY(Module, AutoCSR): p_DELAY_SRC = "IDATAIN", p_DELAY_TYPE = "VARIABLE", p_DELAY_VALUE = 0, - i_CLK = ClockSignal(), - i_INC = 1, - i_EN_VTC = self._en_vtc.storage, i_RST = self._dly_sel.storage[i//8] & self._rdly_dq_rst.re, + i_CLK = ClockSignal(), + i_EN_VTC = self._en_vtc.storage, i_CE = self._dly_sel.storage[i//8] & self._rdly_dq_inc.re, + i_INC = 1, i_IDATAIN = dq_i_nodelay, - o_DATAOUT = dq_i_delayed + o_DATAOUT = dq_i_delayed, ), Instance("IOBUF", i_I = dq_o_delayed, o_O = dq_i_nodelay, i_T = dq_t, - io_IO = pads.dq[i] + io_IO = pads.dq[i], ) ] self.comb += [