From 788b3f6d0292b711abbd273480dd00ef7a25bde8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Wed, 3 Feb 2021 16:06:46 +0100 Subject: [PATCH] modules: modules: add LPDDR4 module --- litedram/modules.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/litedram/modules.py b/litedram/modules.py index 8550625..716ae82 100644 --- a/litedram/modules.py +++ b/litedram/modules.py @@ -964,3 +964,18 @@ class MTA18ASF2G72PZ(DDR4RegisteredModule): "2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=trfc, tFAW=(20, 25), tRAS=32), } speedgrade_timings["default"] = speedgrade_timings["2400"] + +# LPDDR4 ------------------------------------------------------------------------------------------- + +class MT53E256M16D1(SDRAMModule): + memtype = "LPDDR4" + + nbanks = 8 + nrows = 32768 + ncols = 1024 + + technology_timings = _TechnologyTimings(tREFI=32e6/8192, tWTR=(8, 10), tCCD=(8, None), tRRD=(4, 10), tZQCS=None) # TODO: tZQCS + speedgrade_timings = { + "1866": _SpeedgradeTimings(tRP=(3, 21), tRCD=(4, 18), tWR=(4, 18), tRFC=180, tFAW=40, tRAS=(3, 42)), # TODO: tRAS_max + } + speedgrade_timings["default"] = speedgrade_timings["1866"]