From 79314f9549c03150e2bf285fa2dcee56a142c814 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Tue, 12 May 2020 13:18:53 +0200 Subject: [PATCH] frontend/wishbone: fix wdata.valid being high with old data, use cmd.last=1 --- litedram/frontend/wishbone.py | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/litedram/frontend/wishbone.py b/litedram/frontend/wishbone.py index 5286245..a8f8e82 100644 --- a/litedram/frontend/wishbone.py +++ b/litedram/frontend/wishbone.py @@ -28,12 +28,18 @@ class LiteDRAMWishbone2Native(Module): [("data", port_data_width), ("we", port_data_width//8)], ) self.submodules += wdata_converter + wdata_lock = Signal() self.comb += [ - wdata_converter.sink.valid.eq(wishbone.cyc & wishbone.stb & wishbone.we), + wdata_converter.sink.valid.eq(wishbone.cyc & wishbone.stb & wishbone.we & ~wdata_lock), wdata_converter.sink.data.eq(wishbone.dat_w), wdata_converter.sink.we.eq(wishbone.sel), wdata_converter.source.connect(port.wdata) ] + self.sync += [ + If(wdata_converter.sink.valid & wdata_converter.sink.ready, + wdata_lock.eq(1) + ) + ] # Read Datapath ---------------------------------------------------------------------------- rdata_converter = stream.StrideConverter( @@ -55,6 +61,7 @@ class LiteDRAMWishbone2Native(Module): port.cmd.valid.eq(wishbone.cyc & wishbone.stb), port.cmd.we.eq(wishbone.we), port.cmd.addr.eq(wishbone.adr*ratio + count - adr_offset), + port.cmd.last.eq(1), If(port.cmd.valid & port.cmd.ready, NextValue(count, count + 1), If(count == (ratio - 1), @@ -69,6 +76,7 @@ class LiteDRAMWishbone2Native(Module): ) fsm.act("WAIT-WRITE", If(wdata_converter.sink.ready, + NextValue(wdata_lock, 0), wishbone.ack.eq(1), NextState("CMD") )