diff --git a/litedram/phy/kusddrphy.py b/litedram/phy/kusddrphy.py
index 3eb15e1..bc593bb 100644
--- a/litedram/phy/kusddrphy.py
+++ b/litedram/phy/kusddrphy.py
@@ -9,8 +9,6 @@ from litex.soc.interconnect.csr import *
 from litedram.common import PhySettings
 from litedram.phy.dfi import *
 
-# TODO:
-# - test on hardware
 
 class KUSDDRPHY(Module, AutoCSR):
     def __init__(self, pads):
@@ -265,15 +263,15 @@ class KUSDDRPHY(Module, AutoCSR):
                 )
             ]
             self.comb += [
-                self.dfi.phases[0].rddata[i].eq(dq_bitslip.o[7]),
-                self.dfi.phases[1].rddata[i].eq(dq_bitslip.o[5]),
-                self.dfi.phases[2].rddata[i].eq(dq_bitslip.o[3]),
-                self.dfi.phases[3].rddata[i].eq(dq_bitslip.o[1]),
+                self.dfi.phases[0].rddata[i].eq(dq_bitslip.o[0]),
+                self.dfi.phases[1].rddata[i].eq(dq_bitslip.o[2]),
+                self.dfi.phases[2].rddata[i].eq(dq_bitslip.o[4]),
+                self.dfi.phases[3].rddata[i].eq(dq_bitslip.o[6]),
 
-                self.dfi.phases[0].rddata[databits+i].eq(dq_bitslip.o[6]),
-                self.dfi.phases[1].rddata[databits+i].eq(dq_bitslip.o[4]),
-                self.dfi.phases[2].rddata[databits+i].eq(dq_bitslip.o[2]),
-                self.dfi.phases[3].rddata[databits+i].eq(dq_bitslip.o[0]),
+                self.dfi.phases[0].rddata[databits+i].eq(dq_bitslip.o[1]),
+                self.dfi.phases[1].rddata[databits+i].eq(dq_bitslip.o[3]),
+                self.dfi.phases[2].rddata[databits+i].eq(dq_bitslip.o[5]),
+                self.dfi.phases[3].rddata[databits+i].eq(dq_bitslip.o[7]),
             ]
 
         # Flow control