diff --git a/bench/arty.py b/bench/arty.py
index bca303e..0a4f529 100755
--- a/bench/arty.py
+++ b/bench/arty.py
@@ -86,7 +86,7 @@ class BenchSoC(SoCCore):
         )
 
         # UARTBone ---------------------------------------------------------------------------------
-        self.add_uartbone(name="serial", clk_freq=100e6, baudrate=1e6, cd="uart")
+        self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
 
         # Leds -------------------------------------------------------------------------------------
         from litex.soc.cores.led import LedChaser
diff --git a/bench/common.py b/bench/common.py
index 53027c7..e5d3c73 100644
--- a/bench/common.py
+++ b/bench/common.py
@@ -108,7 +108,7 @@ class BenchController:
 
 # Bench Test ---------------------------------------------------------------------------------------
 
-def s7_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_timeout=10):
+def s7_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_timeout=40):
     import time
     from litex import RemoteClient
 
@@ -119,7 +119,7 @@ def s7_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_t
 
     # Load BIOS and reboot SoC
     ctrl = BenchController(bus)
-    ctrl.load_rom(bios_filename)
+    ctrl.load_rom(bios_filename, delay=1e-4) # FIXME: delay needed @ 115200bauds.
     ctrl.reboot()
 
     # PLL/ClkReg
@@ -185,7 +185,7 @@ def us_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_t
 
     # Load BIOS and reboot SoC
     ctrl = BenchController(bus)
-    ctrl.load_rom(bios_filename, delay=1e-4) # FIXME: delay needed on KCU105 @ 11200bauds.
+    ctrl.load_rom(bios_filename, delay=1e-4) # FIXME: delay needed @ 115200bauds.
     ctrl.reboot()
 
     # PLL/ClkReg
diff --git a/bench/genesys2.py b/bench/genesys2.py
index 892e1ca..6013acf 100755
--- a/bench/genesys2.py
+++ b/bench/genesys2.py
@@ -84,7 +84,7 @@ class BenchSoC(SoCCore):
         )
 
         # UARTBone ---------------------------------------------------------------------------------
-        self.add_uartbone(name="serial", clk_freq=100e6, baudrate=1e6, cd="uart")
+        self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
 
         # Leds -------------------------------------------------------------------------------------
         from litex.soc.cores.led import LedChaser
diff --git a/bench/kc705.py b/bench/kc705.py
index b2e0aab..9b893d7 100755
--- a/bench/kc705.py
+++ b/bench/kc705.py
@@ -84,7 +84,7 @@ class BenchSoC(SoCCore):
         )
 
         # UARTBone ---------------------------------------------------------------------------------
-        self.add_uartbone(name="serial", clk_freq=100e6, baudrate=500e3, cd="uart")
+        self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
 
         # Leds -------------------------------------------------------------------------------------
         from litex.soc.cores.led import LedChaser