From 7f742c7fde484ef9408b8486ae10b3c59cbc8993 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Tue, 13 Jul 2021 12:34:22 +0200 Subject: [PATCH] phy/lpddr5/sim: handle data masking during masked-write --- litedram/phy/lpddr5/sim.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/litedram/phy/lpddr5/sim.py b/litedram/phy/lpddr5/sim.py index 626b0f5..ff95c53 100644 --- a/litedram/phy/lpddr5/sim.py +++ b/litedram/phy/lpddr5/sim.py @@ -641,7 +641,11 @@ class BurstHalf(Module): ) ) fsm.act("BURST-WRITE", - ports[cmd_d.bank].we.eq(2**len(ports[cmd_d.bank].we) - 1), + If(cmd_d.masked, + ports[cmd_d.bank].we.eq(~pads.dmi), # DMI HIGH masks a byte + ).Else( + ports[cmd_d.bank].we.eq(2**len(ports[cmd_d.bank].we) - 1), + ), ports[cmd_d.bank].dat_w.eq(pads.dq), self.log.debug("WRITE[%d]: bank=%d, row=%d, col=%d, dq=0x%04x dm=0x%02b", burst_beat, cmd_d.bank, cmd_d.row, current_col, pads.dq, pads.dmi,