From 8122209d9bd74211220367e11a19c07c0e020505 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 26 Feb 2020 15:48:10 +0100
Subject: [PATCH] modules: add MT40A256M16

---
 litedram/modules.py | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/litedram/modules.py b/litedram/modules.py
index 0473bd5..5edf56c 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -541,6 +541,24 @@ class MT40A1G8(SDRAMModule):
     speedgrade_timings["default"] = speedgrade_timings["2400"]
 
 
+class MT40A256M16(SDRAMModule):
+    memtype = "DDR4"
+    # geometry
+    ngroupbanks = 4
+    ngroups     = 2
+    nbanks      = ngroups * ngroupbanks
+    nrows       = 32768
+    ncols       = 1024
+    # timings
+    trefi = {"1x": 64e6/8192, "2x": (64e6/8192)/2, "4x": (64e6/8192)/4}
+    trfc = {"1x": (None, 260), "2x": (None, 160), "4x": (None, 110)}
+    technology_timings = _TechnologyTimings(tREFI=trefi, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 4.9), tZQCS=(128, 80))
+    speedgrade_timings = {
+        "2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=trfc, tFAW=(28, 35), tRAS=32),
+    }
+    speedgrade_timings["default"] = speedgrade_timings["2400"]
+
+
 class MT40A512M16(SDRAMModule):
     memtype = "DDR4"
     # geometry