From 8181fea0da6abd9353c7c7c8887d2eaad9d98285 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 4 Nov 2018 18:50:50 +0100
Subject: [PATCH] modules: add EDY4016A DDR4

---
 litedram/modules.py | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/litedram/modules.py b/litedram/modules.py
index 1bfc532..ee11b3a 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -312,3 +312,19 @@ class MT18KSF1G72HZ(SDRAMModule):
         "1600": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=13.125, tRFC=128, tFAW=(None, 40), tRAS=None),
     }
     speedgrade_timings["default"] = speedgrade_timings["1600"]
+
+
+# DDR4 (Chips)
+class EDY4016A(SDRAMModule):
+    memtype = "DDR4"
+    # geometry
+    nbanks_groups = 2
+    nbanks = 4
+    nrows  = 32768
+    ncols  = 1024
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 4.9))
+    speedgrade_timings = {
+        "2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=260, tFAW=(28, 30), tRAS=32),
+    }
+    speedgrade_timings["default"] = speedgrade_timings["2400"]