From 81d318aa46b58a584b415d49e1bc5661e408ad85 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 26 Nov 2021 11:51:49 +0100
Subject: [PATCH] frontend/dma/LiteDRAMDMAWriter: Set b.ready to 1 on AXI port.

Avoid having to do it externally.
---
 litedram/frontend/dma.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/litedram/frontend/dma.py b/litedram/frontend/dma.py
index dcba915..97897ef 100644
--- a/litedram/frontend/dma.py
+++ b/litedram/frontend/dma.py
@@ -221,6 +221,9 @@ class LiteDRAMDMAWriter(Module, AutoCSR):
             wdata.data.eq(fifo.source.data)
         ]
 
+        if is_axi:
+            self.comb += port.b.ready.eq(1)
+
         if with_csr:
             self.add_csr()