From 82b7199770d5f09b2672b4c2a8e92f7cdcc2ed79 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 6 Jul 2018 14:28:52 +0200 Subject: [PATCH] modules: fix tWTR for DDR3 modules (expressed in sys_clk not ns) --- litedram/modules.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litedram/modules.py b/litedram/modules.py index aee2e1f..769195e 100644 --- a/litedram/modules.py +++ b/litedram/modules.py @@ -214,7 +214,7 @@ class MT41K128M16(SDRAMModule): tRP = 13.75 tRCD = 13.75 tWR = 15 - tWTR = 8 + tWTR = 3 tREFI = 64*1000*1000/8192 tRFC = 160 @@ -229,7 +229,7 @@ class MT41K256M16(SDRAMModule): tRP = 13.75 tRCD = 13.75 tWR = 15 - tWTR = 8 + tWTR = 3 tREFI = 64*1000*1000/8192 tRFC = 260 @@ -244,7 +244,7 @@ class MT41J256M16(SDRAMModule): tRP = 13.75 tRCD = 13.75 tWR = 15 - tWTR = 8 + tWTR = 3 tREFI = 64*1000*1000/8192 tRFC = 260 @@ -259,6 +259,6 @@ class MT18KSF1G72HZ_1G6(SDRAMModule): tRP = 13.75 tRCD = 13.75 tWR = 15 - tWTR = 8 + tWTR = 3 tREFI = 64*1000*1000/8192 tRFC = 260