diff --git a/litedram/frontend/dma.py b/litedram/frontend/dma.py
index 3f31455..f254a2b 100644
--- a/litedram/frontend/dma.py
+++ b/litedram/frontend/dma.py
@@ -46,9 +46,6 @@ class LiteDRAMDMAReader(Module, AutoCSR):
 
     source : Record("data")
         Source for DRAM word results from reading.
-
-    rsv_level: Signal()
-        FIFO reservation level counter
     """
 
     def __init__(self, port, fifo_depth=16, fifo_buffered=False, with_csr=False):