From 8594e12b3a168d3af086117e2ffadb9d9bee1fa9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 13 Feb 2020 16:57:47 +0100 Subject: [PATCH] phy/model: update TODO --- litedram/phy/model.py | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/litedram/phy/model.py b/litedram/phy/model.py index 1bfe6f1..821024f 100644 --- a/litedram/phy/model.py +++ b/litedram/phy/model.py @@ -4,11 +4,7 @@ # SDRAM simulation PHY at DFI level tested with SDR/DDR/DDR2/LPDDR/DDR3 # TODO: -# - test/add DDR4 support. -# - add init/dump capabilities. # - add multirank support. -# - add bandwidth/efficiency measurements. -# - add timings checks. from migen import * @@ -213,7 +209,7 @@ class DFITimingsChecker(Module): val = self.ck_ns_to_ps(val, tck) else: val = self.ns_to_ps(val) - + new_timings[key] = val new_timings['tRC'] = new_timings['tRAS'] + new_timings['tRP']