From 0405f4156de38ad81693153eb11ced90aa47f1a2 Mon Sep 17 00:00:00 2001 From: Date: Tue, 25 Sep 2018 12:06:19 -0400 Subject: [PATCH] Update the write-to-precharge timings so it works with 1:2 --- litedram/core/bankmachine.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/litedram/core/bankmachine.py b/litedram/core/bankmachine.py index 033b637..1c77a34 100644 --- a/litedram/core/bankmachine.py +++ b/litedram/core/bankmachine.py @@ -1,3 +1,4 @@ +import math from migen import * from migen.genlib.misc import WaitTimer @@ -84,7 +85,8 @@ class BankMachine(Module): ] # Respect write-to-precharge specification - precharge_time = 2 + settings.timing.tWR - 1 + 1 + write_latency = math.ceil(settings.phy.cwl / settings.phy.nphases) + precharge_time = write_latency + settings.timing.tWR - 1 + settings.timing.tCCD precharge_timer = WaitTimer(precharge_time) self.submodules += precharge_timer self.comb += precharge_timer.wait.eq(~(cmd.valid & cmd.ready & cmd.is_write))