From 86b0cc0a56763ceb6ec01e770a28231db9d07d71 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 10 Jul 2017 12:02:13 +0200 Subject: [PATCH] frontend/bist: restrict lfsr to 32 bit allow bist with large ddram msbs data are then filled with zeros, but we should fix lfsr generation to avoid this --- litedram/frontend/bist.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litedram/frontend/bist.py b/litedram/frontend/bist.py index 6ed932f..0a30459 100644 --- a/litedram/frontend/bist.py +++ b/litedram/frontend/bist.py @@ -84,7 +84,7 @@ class _LiteDRAMBISTGenerator(Module): # # # gen_cls = LFSR if random else Counter - gen = gen_cls(dram_port.dw) + gen = gen_cls(min(dram_port.dw, 32)) # FIXME: remove lfsr limitation dma = LiteDRAMDMAWriter(dram_port) self.submodules += dma, gen @@ -210,7 +210,7 @@ class _LiteDRAMBISTChecker(Module, AutoCSR): # # # gen_cls = LFSR if random else Counter - gen = gen_cls(dram_port.dw) + gen = gen_cls(min(dram_port.dw, 32)) # FIXME: remove lfsr limitation dma = LiteDRAMDMAReader(dram_port) self.submodules += dma, gen