From 86b3e2d2ef5633a2dec57f7f9ddfbfa2f13eddde Mon Sep 17 00:00:00 2001 From: Date: Fri, 10 Aug 2018 15:54:22 -0400 Subject: [PATCH] Add reorder flag to the crossbar --- litedram/common.py | 8 +++++--- litedram/frontend/crossbar.py | 8 ++++---- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/litedram/common.py b/litedram/common.py index dba45e1..f284c1c 100644 --- a/litedram/common.py +++ b/litedram/common.py @@ -105,7 +105,7 @@ def rdata_description(dw, with_bank): class LiteDRAMPort: def __init__(self, mode, aw, dw, cd="sys", id=0, - with_data_bank=False): + reorder=False): self.mode = mode self.aw = aw self.dw = dw @@ -115,9 +115,11 @@ class LiteDRAMPort: self.lock = Signal() self.cmd = stream.Endpoint(cmd_description(aw)) - self.wdata = stream.Endpoint(wdata_description(dw, with_data_bank)) - self.rdata = stream.Endpoint(rdata_description(dw, with_data_bank)) + self.wdata = stream.Endpoint(wdata_description(dw, reorder)) + self.rdata = stream.Endpoint(rdata_description(dw, reorder)) + if reorder: + print("WARNING: Reordering controller is experimental") self.flush = Signal() diff --git a/litedram/frontend/crossbar.py b/litedram/frontend/crossbar.py index 1936cb5..b1d2df3 100644 --- a/litedram/frontend/crossbar.py +++ b/litedram/frontend/crossbar.py @@ -26,19 +26,19 @@ class LiteDRAMCrossbar(Module): self.masters = [] - def get_port(self, mode="both", dw=None, cd="sys", reverse=False): + def get_port(self, mode="both", dw=None, cd="sys", reverse=False, reorder=False): if self.finalized: raise FinalizeError if dw is None: dw = self.dw # crossbar port - port = LiteDRAMPort(mode, self.rca_bits + self.bank_bits, self.dw, "sys", len(self.masters)) + port = LiteDRAMPort(mode, self.rca_bits + self.bank_bits, self.dw, "sys", len(self.masters), reorder) self.masters.append(port) # clock domain crossing if cd != "sys": - new_port = LiteDRAMPort(mode, port.aw, port.dw, cd, port.id) + new_port = LiteDRAMPort(mode, port.aw, port.dw, cd, port.id, reorder) self.submodules += LiteDRAMPortCDC(new_port, port) port = new_port @@ -48,7 +48,7 @@ class LiteDRAMCrossbar(Module): adr_shift = -log2_int(dw//self.dw) else: adr_shift = log2_int(self.dw//dw) - new_port = LiteDRAMPort(mode, port.aw + adr_shift, dw, cd, port.id) + new_port = LiteDRAMPort(mode, port.aw + adr_shift, dw, cd, port.id, reorder) self.submodules += ClockDomainsRenamer(cd)(LiteDRAMPortConverter(new_port, port, reverse)) port = new_port