From 873b970fcaba16f07b262df4e3361bdd294a0dbf Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 9 Aug 2018 09:33:24 +0200 Subject: [PATCH] frontend: avoid breaking api with last rbank change (use bankbits_max), some cleanup --- litedram/common.py | 24 ++++++++++++++---------- litedram/frontend/crossbar.py | 13 +++++-------- 2 files changed, 19 insertions(+), 18 deletions(-) diff --git a/litedram/common.py b/litedram/common.py index e5b600e..989b833 100644 --- a/litedram/common.py +++ b/litedram/common.py @@ -1,6 +1,10 @@ from migen import * from litex.soc.interconnect import stream + +bankbits_max = 3 + + class PhySettings: def __init__(self, memtype, dfi_databits, nphases, @@ -56,12 +60,12 @@ def cmd_layout(aw): ] -def data_layout(dw, bankbits): +def data_layout(dw): return [ - ("wdata", dw, DIR_M_TO_S), - ("wdata_we", dw//8, DIR_M_TO_S), - ("rdata", dw, DIR_S_TO_M), - ("rbank", bankbits, DIR_S_TO_M) + ("wdata", dw, DIR_M_TO_S), + ("wdata_we", dw//8, DIR_M_TO_S), + ("rdata", dw, DIR_S_TO_M), + ("rbank", bankbits_max, DIR_S_TO_M) ] @@ -73,7 +77,7 @@ class LiteDRAMInterface(Record): self.settings = settings layout = [("bank"+str(i), cmd_layout(self.aw)) for i in range(self.nbanks)] - layout += data_layout(self.dw, settings.geom.bankbits) + layout += data_layout(self.dw) Record.__init__(self, layout) def cmd_description(aw): @@ -88,12 +92,12 @@ def wdata_description(dw): ("we", dw//8) ] -def rdata_description(dw, nbanks): - return [("data", dw), ("bank", nbanks)] +def rdata_description(dw): + return [("data", dw), ("bank", bankbits_max)] class LiteDRAMPort: - def __init__(self, mode, aw, dw, bankbits, cd="sys", id=0): + def __init__(self, mode, aw, dw, cd="sys", id=0): self.mode = mode self.aw = aw self.dw = dw @@ -104,7 +108,7 @@ class LiteDRAMPort: self.cmd = stream.Endpoint(cmd_description(aw)) self.wdata = stream.Endpoint(wdata_description(dw)) - self.rdata = stream.Endpoint(rdata_description(dw, bankbits)) + self.rdata = stream.Endpoint(rdata_description(dw)) self.flush = Signal() diff --git a/litedram/frontend/crossbar.py b/litedram/frontend/crossbar.py index ed7fc27..35c6adb 100644 --- a/litedram/frontend/crossbar.py +++ b/litedram/frontend/crossbar.py @@ -33,12 +33,12 @@ class LiteDRAMCrossbar(Module): dw = self.dw # crossbar port - port = LiteDRAMPort(mode, self.rca_bits + self.bank_bits, self.dw, self.bank_bits, "sys", len(self.masters)) + port = LiteDRAMPort(mode, self.rca_bits + self.bank_bits, self.dw, "sys", len(self.masters)) self.masters.append(port) # clock domain crossing if cd != "sys": - new_port = LiteDRAMPort(mode, port.aw, port.dw, self.bank_bits, cd, port.id) + new_port = LiteDRAMPort(mode, port.aw, port.dw, cd, port.id) self.submodules += LiteDRAMPortCDC(new_port, port) port = new_port @@ -48,7 +48,7 @@ class LiteDRAMCrossbar(Module): adr_shift = -log2_int(dw//self.dw) else: adr_shift = log2_int(self.dw//dw) - new_port = LiteDRAMPort(mode, port.aw + adr_shift, dw, self.bank_bits, cd, port.id) + new_port = LiteDRAMPort(mode, port.aw + adr_shift, dw, cd, port.id) self.submodules += ClockDomainsRenamer(cd)(LiteDRAMPortConverter(new_port, port, reverse)) port = new_port @@ -68,7 +68,7 @@ class LiteDRAMCrossbar(Module): arbiters = [roundrobin.RoundRobin(nmasters, roundrobin.SP_CE) for n in range(self.nbanks)] self.submodules += arbiters - + rbank = Signal(max=self.nbanks) for nb, arbiter in enumerate(arbiters): bank = getattr(controller, "bank"+str(nb)) @@ -92,10 +92,7 @@ class LiteDRAMCrossbar(Module): ] # Get rdata source bank - self.sync += \ - If((arbiter.grant == nm) & bank.rdata_valid, - rbank.eq(nb) - ) + self.sync += If((arbiter.grant == nm) & bank.rdata_valid, rbank.eq(nb)) # route requests self.comb += [