From ec37a6353bab7e76dfdb14281f5fc230535eb2bf Mon Sep 17 00:00:00 2001
From: "Nathaniel R. Lewis" <linux.robotdude@gmail.com>
Date: Sun, 15 Nov 2020 22:12:32 -0800
Subject: [PATCH] modules: add MT48LC32M8 SDR module

---
 litedram/modules.py | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/litedram/modules.py b/litedram/modules.py
index 36c3e5c..7383cce 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -461,6 +461,15 @@ class MT48LC16M16(SDRModule):
     technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 15))
     speedgrade_timings = {"default": _SpeedgradeTimings(tRP=20, tRCD=20, tWR=15, tRFC=(None, 66), tFAW=None, tRAS=44)}
 
+class MT48LC32M8(SDRModule):
+    # geometry
+    nbanks = 4
+    nrows  = 8192
+    ncols  = 1024
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 15))
+    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=20, tRCD=20, tWR=15, tRFC=(None, 66), tFAW=None, tRAS=44)}
+
 class AS4C16M16(SDRModule):
     # geometry
     nbanks = 4