From 883e97101a06d29fbe0b4403e41b45d1665d47b8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 27 Jun 2017 15:06:12 +0200 Subject: [PATCH] common: add id to ports --- litedram/common.py | 3 ++- litedram/frontend/crossbar.py | 6 +++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/litedram/common.py b/litedram/common.py index 40d88c3..769071e 100644 --- a/litedram/common.py +++ b/litedram/common.py @@ -89,11 +89,12 @@ def rdata_description(dw): class LiteDRAMPort: - def __init__(self, mode, aw, dw, cd="sys"): + def __init__(self, mode, aw, dw, cd="sys", id=0): self.mode = mode self.aw = aw self.dw = dw self.cd = cd + self.id = id self.lock = Signal() diff --git a/litedram/frontend/crossbar.py b/litedram/frontend/crossbar.py index a77bd10..5c2a385 100644 --- a/litedram/frontend/crossbar.py +++ b/litedram/frontend/crossbar.py @@ -33,12 +33,12 @@ class LiteDRAMCrossbar(Module): dw = self.dw # crossbar port - port = LiteDRAMPort(mode, self.rca_bits + self.bank_bits, self.dw, "sys") + port = LiteDRAMPort(mode, self.rca_bits + self.bank_bits, self.dw, "sys", len(self.masters)) self.masters.append(port) # clock domain crossing if cd != "sys": - new_port = LiteDRAMPort(mode, port.aw, port.dw, cd) + new_port = LiteDRAMPort(mode, port.aw, port.dw, cd, port.id) self.submodules += LiteDRAMPortCDC(new_port, port) port = new_port @@ -48,7 +48,7 @@ class LiteDRAMCrossbar(Module): adr_shift = -log2_int(dw//self.dw) else: adr_shift = log2_int(self.dw//dw) - new_port = LiteDRAMPort(mode, port.aw + adr_shift, dw, cd=cd) + new_port = LiteDRAMPort(mode, port.aw + adr_shift, dw, cd, port.id) self.submodules += ClockDomainsRenamer(cd)(LiteDRAMPortConverter(new_port, port, reverse)) port = new_port