diff --git a/litedram/modules.py b/litedram/modules.py
index 8737fc6..0c1ce88 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -218,6 +218,17 @@ class MT47H128M8(SDRAMModule):
     speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 127.5), tFAW=None, tRAS=None)}
 
 
+class MT47H32M16(SDRAMModule):
+    memtype = "DDR2"
+    # geometry
+    nbanks = 4
+    nrows  = 8192
+    ncols  = 1024
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(None, 7.5), tCCD=(2, None), tRRD=None)
+    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 127.5), tFAW=None, tRAS=None)}
+
+
 class MT47H64M16(SDRAMModule):
     memtype = "DDR2"
     # geometry