diff --git a/test/reference/ddr3_init.h b/test/reference/ddr3_init.h
index cf88de7..ac3e5c4 100644
--- a/test/reference/ddr3_init.h
+++ b/test/reference/ddr3_init.h
@@ -25,9 +25,10 @@
 #define SDRAM_PHY_RDPHASE 1
 #define SDRAM_PHY_WRPHASE 2
 #define SDRAM_PHY_WRITE_LEVELING_CAPABLE
+#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE
 #define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE
 #define SDRAM_PHY_READ_LEVELING_CAPABLE
-#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2
+#define SDRAM_PHY_MODULES SDRAM_PHY_DATABITS/8
 #define SDRAM_PHY_DELAYS 32
 #define SDRAM_PHY_BITSLIPS 8
 
diff --git a/test/reference/ddr4_init.h b/test/reference/ddr4_init.h
index ec7232f..b13055d 100644
--- a/test/reference/ddr4_init.h
+++ b/test/reference/ddr4_init.h
@@ -25,9 +25,10 @@
 #define SDRAM_PHY_RDPHASE 3
 #define SDRAM_PHY_WRPHASE 3
 #define SDRAM_PHY_WRITE_LEVELING_CAPABLE
+#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE
 #define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE
 #define SDRAM_PHY_READ_LEVELING_CAPABLE
-#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2
+#define SDRAM_PHY_MODULES SDRAM_PHY_DATABITS/8
 #define SDRAM_PHY_DELAYS 512
 #define SDRAM_PHY_BITSLIPS 8
 
diff --git a/test/reference/sdr_init.h b/test/reference/sdr_init.h
index 69bc521..ced1036 100644
--- a/test/reference/sdr_init.h
+++ b/test/reference/sdr_init.h
@@ -23,6 +23,7 @@
 #define SDRAM_PHY_CWL 2
 #define SDRAM_PHY_RDPHASE 0
 #define SDRAM_PHY_WRPHASE 0
+#define SDRAM_PHY_MODULES SDRAM_PHY_DATABITS/8
 
 static void cdelay(int i);