From f3f89ed8d101fc021e1ad3f147a4bc5120c557c5 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Mon, 1 Jun 2020 20:13:59 +1000 Subject: [PATCH] Default to HW control for sim (needs corresponding sdram.c fix in litex) Signed-off-by: Benjamin Herrenschmidt --- litedram/dfii.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/litedram/dfii.py b/litedram/dfii.py index 9467299..538e478 100644 --- a/litedram/dfii.py +++ b/litedram/dfii.py @@ -49,7 +49,11 @@ class DFIInjector(Module, AutoCSR): self.slave = dfi.Interface(addressbits, bankbits, nranks, databits, nphases) self.master = dfi.Interface(addressbits, bankbits, nranks, databits, nphases) - self._control = CSRStorage(4) # sel, cke, odt, reset_n + # sel, cke, odt, reset_n + # + # sel defaults 1 (HW control) so sim models don't need to perform + # the initialization sequence + self._control = CSRStorage(4, reset=0x01) for n, phase in enumerate(inti.phases): setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))