phy/utils: DFI rate converter for creating PHY wrappers at slower clocks
This commit is contained in:
Jędrzej Boczar
parent
46ea844702
commit
89af25a697
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@ -2,11 +2,14 @@
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
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# Copyright (c) 2021 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.record import *
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from litedram.phy.utils import Serializer, Deserializer
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def phase_cmd_description(addressbits, bankbits, nranks):
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return [
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@ -97,3 +100,130 @@ class DDR4DFIMux(Module):
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p_o.act_n.eq(1),
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)
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]
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class DFIRateConverter(Module):
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"""Converts between DFI interfaces running at different clock frequencies
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This module allows to convert DFI interface `phy_dfi` running at higher clock frequency
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into a DFI interface running at `ratio` lower frequency. The new DFI has `ratio` more
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phases and the commands on the following phases of the new DFI will be serialized to
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following phases/clocks of `phy_dfi` (phases first, then clock cycles).
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Data must be serialized/deserialized in such a way that a whole burst on `phy_dfi` is
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sent in a single `clk` cycle. For this reason, the new DFI interface will have `ratio`
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less databits. For example, with phy_dfi(nphases=2, databits=32) and ratio=4 the new
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DFI will have nphases=8, databits=8. This results in 8*8=64 bits in `clkdiv` translating
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into 2*32=64 bits in `clk`. This means that only a single cycle of `clk` per `clkdiv`
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cycle carries the data (by default cycle 0). This can be modified by passing values
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different than 0 for `write_delay`/`read_delay` and may be needed to properly align
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write/read latency of the original PHY and the wrapper.
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"""
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def __init__(self, phy_dfi, *, clkdiv, clk, ratio, serdes_reset_cnt=-1, write_delay=0, read_delay=0):
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assert len(phy_dfi.p0.wrdata) % ratio == 0
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assert 0 <= write_delay < ratio, f"Data can be delayed up to {ratio} clk cycles"
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assert 0 <= read_delay < ratio, f"Data can be delayed up to {ratio} clk cycles"
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self.ser_latency = Serializer.LATENCY
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self.des_latency = Deserializer.LATENCY
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phase_params = dict(
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addressbits = len(phy_dfi.p0.address),
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bankbits = len(phy_dfi.p0.bank),
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nranks = len(phy_dfi.p0.cs_n),
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databits = len(phy_dfi.p0.wrdata) // ratio,
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)
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self.dfi = Interface(nphases=ratio * len(phy_dfi.phases), **phase_params)
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wr_delayed = ["wrdata", "wrdata_mask"]
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rd_delayed = ["rddata", "rddata_valid"]
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for name, width, dir in phase_description(**phase_params):
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# all signals except write/read
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if name in wr_delayed + rd_delayed:
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continue
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# on each clk phase
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for pi, phase_s in enumerate(phy_dfi.phases):
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sig_s = getattr(phase_s, name)
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assert len(sig_s) == width
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# data from each clkdiv phase
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sigs_m = []
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for j in range(ratio):
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phase_m = self.dfi.phases[pi + len(phy_dfi.phases)*j]
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sigs_m.append(getattr(phase_m, name))
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ser = Serializer(
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clkdiv = clkdiv,
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clk = clk,
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i_dw = ratio*width,
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o_dw = width,
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i = Cat(sigs_m),
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o = sig_s,
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reset_cnt = serdes_reset_cnt,
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name = name,
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)
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self.submodules += ser
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# wrdata
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for name, width, dir in phase_description(**phase_params):
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if name not in wr_delayed:
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continue
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for pi, phase_s in enumerate(phy_dfi.phases):
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sig_s = getattr(phase_s, name)
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sig_m = Signal(len(sig_s) * ratio)
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sigs_m = []
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for j in range(ratio):
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phase_m = self.dfi.phases[pi*ratio + j]
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sigs_m.append(getattr(phase_m, name))
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width = len(Cat(sigs_m))
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self.comb += sig_m[write_delay*width:(write_delay+1)*width].eq(Cat(sigs_m))
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o = Signal.like(sig_s)
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ser = Serializer(
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clkdiv = clkdiv,
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clk = clk,
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i_dw = len(sig_m),
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o_dw = len(sig_s),
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i = sig_m,
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o = o,
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reset_cnt = serdes_reset_cnt,
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name = name,
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)
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self.submodules += ser
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self.comb += sig_s.eq(o)
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# rddata
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for name, width, dir in phase_description(**phase_params):
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if name not in rd_delayed:
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continue
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for pi, phase_s in enumerate(phy_dfi.phases):
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sig_s = getattr(phase_s, name)
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sig_m = Signal(ratio * len(sig_s))
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sigs_m = []
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for j in range(ratio):
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phase_m = self.dfi.phases[pi*ratio + j]
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sigs_m.append(getattr(phase_m, name))
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des = Deserializer(
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clkdiv = clkdiv,
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clk = clk,
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i_dw = len(sig_s),
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o_dw = len(sig_m),
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i = sig_s,
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o = sig_m,
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reset_cnt = serdes_reset_cnt,
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name = name,
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)
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self.submodules += des
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if name == "rddata_valid":
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self.comb += Cat(sigs_m).eq(Replicate(sig_m[read_delay], ratio))
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else:
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out_width = len(Cat(sigs_m))
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sig_m_window = sig_m[read_delay*out_width:(read_delay + 1)*out_width]
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self.comb += Cat(sigs_m).eq(sig_m_window)
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@ -228,8 +228,8 @@ class Serializer(Module):
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LATENCY = 1
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def __init__(self, clkdiv, clk, i_dw, o_dw, i=None, o=None, reset=None, reset_cnt=-1, name=None):
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assert i_dw > o_dw
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assert i_dw % o_dw == 0
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assert i_dw > o_dw, (i_dw, o_dw)
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assert i_dw % o_dw == 0, (i_dw, o_dw)
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ratio = i_dw // o_dw
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sd_clk = getattr(self.sync, clk)
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@ -271,8 +271,8 @@ class Deserializer(Module):
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LATENCY = 2
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def __init__(self, clkdiv, clk, i_dw, o_dw, i=None, o=None, reset=None, reset_cnt=-1, name=None):
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assert i_dw < o_dw
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assert o_dw % i_dw == 0
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assert i_dw < o_dw, (i_dw, o_dw)
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assert o_dw % i_dw == 0, (i_dw, o_dw)
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ratio = o_dw // i_dw
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sd_clk = getattr(self.sync, clk)
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@ -179,6 +179,9 @@ def dfi_names(cmd=True, wrdata=True, rddata=True):
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if rddata: names += [name for name, _, _ in dfi.phase_rddata_description(16)]
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return names
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def dfi_reset_values(**kwargs):
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return {sig: 1 if sig.endswith("_n") else 0 for sig in dfi_names(**kwargs)}
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class DFIPhaseValues(dict):
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"""Dictionary {dfi_signal_name: value}"""
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@ -219,12 +222,9 @@ class DFISequencer:
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def add(self, dfi_cycle: Mapping[DFIPhase, DFIPhaseValues]):
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self.sequence.append(dfi_cycle)
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def _dfi_reset_values(self):
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return {sig: 1 if sig.endswith("_n") else 0 for sig in dfi_names()}
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def _reset(self, dfi):
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for phase in dfi.phases:
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for sig, val in self._dfi_reset_values().items():
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for sig, val in dfi_reset_values().items():
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yield getattr(phase, sig).eq(val)
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def assert_ok(self, test_case):
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@ -268,3 +268,19 @@ class DFISequencer:
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phases[i] = values
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self.read_sequence.append(phases)
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yield
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@staticmethod
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def input_generator(dfi, sequence: DFISequence):
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names = dfi_names(cmd=True, wrdata=True, rddata=False) + ["rddata_en"]
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for per_phase in sequence:
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# set values
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for phase, values in per_phase.items():
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for sig, val in values.items():
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assert sig not in names, f"`{sig}` is not DFI input signal"
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yield getattr(dfi.phases[phase], sig).eq(val)
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yield
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# reset values
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for phase, values in per_phase.items():
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for sig in values.keys():
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yield getattr(dfi.phases[phase], sig).eq(0)
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yield
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@ -0,0 +1,489 @@
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#
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2021 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import unittest
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from collections import defaultdict
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from migen import *
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from litex.build.sim import gtkwave as gtkw
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from litedram.phy.dfi import Interface as DFIInterface, DFIRateConverter
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from litedram.phy.utils import Serializer, Deserializer
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from test.phy_common import DFISequencer, dfi_reset_values, run_simulation as _run_simulation
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def run_simulation(ratio, *args, **kwargs):
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clkdiv = "sys"
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clk = f"sys{ratio}x"
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kwargs["clocks"] = {
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clkdiv: (4*ratio, 4*ratio/2 - 1),
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clk: (4, 1),
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}
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_run_simulation(*args, **kwargs)
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# To debug the tests pass vcd_name="sim.vcd" to the self.run_test call and use `gtkwave sim.gtkw` to view the trace
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class TestPHYRateConverter(unittest.TestCase):
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class Dut(Module):
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def __init__(self, ratio, converter_kwargs=None, **dfi_kwargs):
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self.ratio = ratio
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self.dfi_old = DFIInterface(**dfi_kwargs)
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converter_kwargs = converter_kwargs or {}
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self.submodules.converter = DFIRateConverter(self.dfi_old, clkdiv="sys", clk=f"sys{ratio}x",
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ratio=ratio, serdes_reset_cnt=-1, **converter_kwargs)
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self.dfi = self.converter.dfi
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def dfi_latency(self, ratio, reset_n=True):
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latency_clkdiv = Serializer.LATENCY
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latency_clk = ratio * latency_clkdiv
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nop = {p: (dict(reset_n=0) if reset_n else {}) for p in range(4)} # reset_n will have wrong value until driven
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return [nop] * latency_clk
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def run_test(self, dut, dfi_sys, dfi_expected, dfi_input=None, **kwargs):
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assert callable(dut), "dut must be a callable that returns new Dut instance"
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dfi = DFISequencer(dfi_sys)
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# Add GTKWave savefile for debugging if we are creating a VCD dumpfile (requires pyvcd installed)
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if kwargs.get("vcd_name", False):
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dumpfile = kwargs["vcd_name"]
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savefile = os.path.splitext(dumpfile)[0] + ".gtkw"
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# Create a separate dut just for the purpose of generaing a savefile
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tmp_dut = dut()
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vns = verilog.convert(tmp_dut).ns
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with gtkw.GTKWSave(vns, savefile=savefile, dumpfile=dumpfile, prefix="") as save:
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save.clocks()
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for grp_dfi, grp_name in [(tmp_dut.dfi, "dfi new"), (tmp_dut.dfi_old, "dfi old")]:
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with save.gtkw.group(grp_name):
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# each phase in separate group
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with save.gtkw.group("dfi phaseX", closed=True):
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for i, phase in enumerate(grp_dfi.phases):
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save.add(phase, group_name="dfi p{}".format(i), mappers=[
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gtkw.dfi_sorter(phases=False),
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gtkw.dfi_in_phase_colorer(),
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])
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# only dfi command signals
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save.add(grp_dfi, group_name="dfi commands", mappers=[
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gtkw.regex_filter(gtkw.suffixes2re(["cas_n", "ras_n", "we_n"])),
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gtkw.dfi_sorter(),
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gtkw.dfi_per_phase_colorer(),
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])
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# only dfi data signals
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save.add(grp_dfi, group_name="dfi wrdata", mappers=[
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gtkw.regex_filter(["wrdata$"]),
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gtkw.dfi_sorter(),
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gtkw.dfi_per_phase_colorer(),
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])
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save.add(grp_dfi, group_name="dfi wrdata_mask", mappers=[
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gtkw.regex_filter(gtkw.suffixes2re(["wrdata_mask"])),
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gtkw.dfi_sorter(),
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gtkw.dfi_per_phase_colorer(),
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])
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save.add(grp_dfi, group_name="dfi rddata", mappers=[
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gtkw.regex_filter(gtkw.suffixes2re(["rddata", "p0.*rddata_valid"])),
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gtkw.dfi_sorter(),
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gtkw.dfi_per_phase_colorer(),
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])
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def checker(dfi):
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fail = False
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history = defaultdict(list)
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reference = defaultdict(list)
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# first cycle has undefined data until DFISequencer drives the signals
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yield
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for i, dfi_phases in enumerate(dfi_expected):
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for phase in range(len(dfi.phases)):
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values = dfi_reset_values()
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values.update(dfi_phases.get(phase, {}))
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for name, ref in values.items():
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# if name in ["rddata", "rddata_valid"]:
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# continue
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val = (yield getattr(dfi.phases[phase], name))
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msg = f"Cycle {i}, dfi.p{phase}.{name} = {val} != {ref}"
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history[name].append(val)
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reference[name].append(ref)
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if not fail and val != ref:
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fail = (val, ref, msg)
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yield
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def split_cycles(hist):
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s = ""
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for i, val in enumerate(hist):
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s += str(val)
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if (i + 1) % len(dfi.phases) == 0:
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s += " "
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return s
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if fail:
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print()
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for sig in history:
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if len(getattr(dfi.phases[0], sig)) == 1:
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print(f"{sig:12}: {split_cycles(history[sig])}")
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print(" "*14 + f"{split_cycles(reference[sig])}")
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self.assertEqual(*fail)
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dut = dut()
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run_simulation(dut.ratio, dut, generators={
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"sys": [dfi.generator(dut.dfi), dfi.reader(dut.dfi)],
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f"sys{dut.ratio}x": [checker(dut.dfi_old), DFISequencer.input_generator(dut.dfi_old, dfi_input or [])],
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}, **kwargs)
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dfi.assert_ok(self)
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def test_dfi_rate_converter_phase_0(self):
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read = dict(cs_n=0, cas_n=0, ras_n=1, we_n=1, bank=0b111, address=0b110101)
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dfi_sys = [
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{0: read},
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]
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dfi_expected = [
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*self.dfi_latency(ratio=2),
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{0: read},
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{},
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]
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self.run_test(lambda: self.Dut(
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ratio=2,
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addressbits=16,
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bankbits=3,
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nranks=1,
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databits=2*16,
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nphases=4,
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), dfi_sys, dfi_expected)
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def test_dfi_rate_converter_1_to_2_cmd(self):
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read = dict(cs_n=0, cas_n=0, ras_n=1, we_n=1, bank=0b111, address=0b110101)
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activate = dict(cs_n=0, cas_n=1, ras_n=0, we_n=1, bank=0b010, address=0b1110000111100001)
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precharge = dict(cs_n=0, cas_n=1, ras_n=0, we_n=0, bank=0b111, address=0)
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dfi_sys = [
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{1: activate, 3: read, 6: precharge},
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]
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dfi_expected = [
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*self.dfi_latency(ratio=2),
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{1: activate, 3: read},
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{2: precharge},
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{}, {}, # 1
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]
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self.run_test(lambda: self.Dut(
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ratio=2,
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addressbits=16,
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bankbits=3,
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nranks=1,
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databits=2*16,
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nphases=4,
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), dfi_sys, dfi_expected)
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def test_dfi_rate_converter_1_to_2_write(self):
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write_ap = dict(cs_n=0, cas_n=0, ras_n=1, we_n=0, bank=0b111, address=0b10000000000, wrdata_en=1)
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data_clkdiv = {
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0: dict(wrdata=0x1111, wrdata_mask=0b00),
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1: dict(wrdata=0x2222, wrdata_mask=0b11),
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2: dict(wrdata=0x3333, wrdata_mask=0b00),
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3: dict(wrdata=0x4444, wrdata_mask=0b11),
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4: dict(wrdata=0x5555, wrdata_mask=0b01),
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5: dict(wrdata=0x6666, wrdata_mask=0b01),
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6: dict(wrdata=0x7777, wrdata_mask=0b10),
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7: dict(wrdata=0x8888, wrdata_mask=0b01),
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}
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data_clk = {
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0: dict(wrdata=0x22221111, wrdata_mask=0b1100),
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1: dict(wrdata=0x44443333, wrdata_mask=0b1100),
|
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2: dict(wrdata=0x66665555, wrdata_mask=0b0101),
|
||||
3: dict(wrdata=0x88887777, wrdata_mask=0b0110),
|
||||
}
|
||||
dfi_sys = [
|
||||
{7: write_ap},
|
||||
{},
|
||||
data_clkdiv,
|
||||
]
|
||||
dfi_expected = [
|
||||
*self.dfi_latency(ratio=2),
|
||||
{}, # 0
|
||||
{3: write_ap},
|
||||
{}, # 1
|
||||
{},
|
||||
data_clk, # 2 (assuming write latency = 3)
|
||||
{},
|
||||
{}, # 3
|
||||
{},
|
||||
]
|
||||
self.run_test(lambda: self.Dut(
|
||||
ratio=2,
|
||||
addressbits=16,
|
||||
bankbits=3,
|
||||
nranks=1,
|
||||
databits=2*16,
|
||||
nphases=4,
|
||||
), dfi_sys, dfi_expected)
|
||||
|
||||
def test_dfi_rate_converter_1_to_2_read(self):
|
||||
read = dict(cs_n=0, cas_n=0, ras_n=1, we_n=1, bank=0b111, address=0b110101)
|
||||
data_clkdiv = {
|
||||
0: dict(rddata=0x1111, rddata_valid=1),
|
||||
1: dict(rddata=0x2222),
|
||||
2: dict(rddata=0x3333),
|
||||
3: dict(rddata=0x4444),
|
||||
4: dict(rddata=0x5555),
|
||||
5: dict(rddata=0x6666),
|
||||
6: dict(rddata=0x7777),
|
||||
7: dict(rddata=0x8888),
|
||||
}
|
||||
data_clk = {
|
||||
0: dict(rddata=0x22221111, rddata_valid=1),
|
||||
1: dict(rddata=0x44443333),
|
||||
2: dict(rddata=0x66665555),
|
||||
3: dict(rddata=0x88887777),
|
||||
}
|
||||
des_latency = [{}] * Deserializer.LATENCY
|
||||
dfi_sys = [
|
||||
{7: read}, # 0
|
||||
{},
|
||||
{}, # 2 (data_clk)
|
||||
*des_latency,
|
||||
data_clkdiv,
|
||||
]
|
||||
dfi_expected = [ # sys2x
|
||||
*self.dfi_latency(ratio=2),
|
||||
{}, # 0
|
||||
{3: read},
|
||||
]
|
||||
dfi_input = [ # sys2x
|
||||
*self.dfi_latency(ratio=2, reset_n=False),
|
||||
{}, # 0
|
||||
{}, # read
|
||||
{}, # 1
|
||||
{},
|
||||
data_clk, # 2 (assumig read latency = 3)
|
||||
]
|
||||
self.run_test(lambda: self.Dut(
|
||||
ratio=2,
|
||||
addressbits=16,
|
||||
bankbits=3,
|
||||
nranks=1,
|
||||
databits=2*16,
|
||||
nphases=4,
|
||||
), dfi_sys, dfi_expected, dfi_input=dfi_input)
|
||||
|
||||
def test_dfi_rate_converter_1_to_4_cmd(self):
|
||||
read = dict(cs_n=0, cas_n=0, ras_n=1, we_n=1, bank=0b111, address=0b110101)
|
||||
activate = dict(cs_n=0, cas_n=1, ras_n=0, we_n=1, bank=0b010, address=0b1110000111100001)
|
||||
precharge = dict(cs_n=0, cas_n=1, ras_n=0, we_n=0, bank=0b111, address=0)
|
||||
dfi_sys = [
|
||||
{1: activate, 3: read, 6: precharge},
|
||||
]
|
||||
dfi_expected = [
|
||||
*self.dfi_latency(ratio=4),
|
||||
{1: activate}, # 0
|
||||
{1: read},
|
||||
{},
|
||||
{0: precharge},
|
||||
{}, {}, {}, {}, # 1
|
||||
]
|
||||
self.run_test(lambda: self.Dut(
|
||||
ratio=4,
|
||||
addressbits=16,
|
||||
bankbits=3,
|
||||
nranks=1,
|
||||
databits=2*16,
|
||||
nphases=2,
|
||||
), dfi_sys, dfi_expected)
|
||||
|
||||
def test_dfi_rate_converter_1_to_4_write(self):
|
||||
write_ap = dict(cs_n=0, cas_n=0, ras_n=1, we_n=0, bank=0b111, address=0b10000000000, wrdata_en=1)
|
||||
data_clkdiv = {
|
||||
0: dict(wrdata=0x11),
|
||||
1: dict(wrdata=0x22),
|
||||
2: dict(wrdata=0x33),
|
||||
3: dict(wrdata=0x44),
|
||||
4: dict(wrdata=0x55),
|
||||
5: dict(wrdata=0x66),
|
||||
6: dict(wrdata=0x77),
|
||||
7: dict(wrdata=0x88),
|
||||
}
|
||||
data_clk = {
|
||||
0: dict(wrdata=0x44332211),
|
||||
1: dict(wrdata=0x88776655),
|
||||
}
|
||||
dfi_sys = [
|
||||
{7: write_ap},
|
||||
{},
|
||||
data_clkdiv,
|
||||
]
|
||||
dfi_expected = [
|
||||
*self.dfi_latency(ratio=4),
|
||||
{}, # 0
|
||||
{},
|
||||
{},
|
||||
{1: write_ap},
|
||||
{}, {}, {}, {}, # 1
|
||||
data_clk, # 2 (assuming write latency = 5)
|
||||
{}, {}, {},
|
||||
{}, {}, {}, {}, # 3
|
||||
]
|
||||
self.run_test(lambda: self.Dut(
|
||||
ratio=4,
|
||||
addressbits=16,
|
||||
bankbits=3,
|
||||
nranks=1,
|
||||
databits=2*16,
|
||||
nphases=2,
|
||||
), dfi_sys, dfi_expected)
|
||||
|
||||
def test_dfi_rate_converter_1_to_4_read(self):
|
||||
read = dict(cs_n=0, cas_n=0, ras_n=1, we_n=1, bank=0b111, address=0b110101)
|
||||
data_clkdiv = {
|
||||
0: dict(rddata=0x1111, rddata_valid=1),
|
||||
1: dict(rddata=0x2222, rddata_valid=1),
|
||||
2: dict(rddata=0x3333, rddata_valid=1),
|
||||
3: dict(rddata=0x4444, rddata_valid=1),
|
||||
4: dict(rddata=0x5555, rddata_valid=1),
|
||||
5: dict(rddata=0x6666, rddata_valid=1),
|
||||
6: dict(rddata=0x7777, rddata_valid=1),
|
||||
7: dict(rddata=0x8888, rddata_valid=1),
|
||||
}
|
||||
data_clk = {
|
||||
0: dict(rddata=0x4444333322221111, rddata_valid=1),
|
||||
1: dict(rddata=0x8888777766665555, rddata_valid=1),
|
||||
}
|
||||
des_latency = [{}] * Deserializer.LATENCY
|
||||
dfi_sys = [
|
||||
{7: read}, # 0
|
||||
{},
|
||||
{}, # 2 (data_clk)
|
||||
*des_latency,
|
||||
data_clkdiv,
|
||||
]
|
||||
dfi_expected = [ # sys2x
|
||||
*self.dfi_latency(ratio=4),
|
||||
{}, # 0
|
||||
{},
|
||||
{},
|
||||
{1: read},
|
||||
]
|
||||
dfi_input = [ # sys2x
|
||||
*self.dfi_latency(ratio=4, reset_n=False),
|
||||
{}, # 0
|
||||
{},
|
||||
{},
|
||||
{}, # read
|
||||
{}, {}, {}, {}, # 1
|
||||
data_clk, # 2 (assumig read latency = 5)
|
||||
]
|
||||
self.run_test(lambda: self.Dut(
|
||||
ratio=4,
|
||||
addressbits=16,
|
||||
bankbits=3,
|
||||
nranks=1,
|
||||
databits=2*32,
|
||||
nphases=2,
|
||||
), dfi_sys, dfi_expected, dfi_input=dfi_input)
|
||||
|
||||
def test_dfi_rate_converter_1_to_4_write_delayed(self):
|
||||
# When write_latency does not aligh with clkdiv boundaries, the write data must be delayed
|
||||
write_ap = dict(cs_n=0, cas_n=0, ras_n=1, we_n=0, bank=0b111, address=0b10000000000, wrdata_en=1)
|
||||
data_clkdiv = {
|
||||
0: dict(wrdata=0x11),
|
||||
1: dict(wrdata=0x22),
|
||||
2: dict(wrdata=0x33),
|
||||
3: dict(wrdata=0x44),
|
||||
4: dict(wrdata=0x55),
|
||||
5: dict(wrdata=0x66),
|
||||
6: dict(wrdata=0x77),
|
||||
7: dict(wrdata=0x88),
|
||||
}
|
||||
data_clk = {
|
||||
0: dict(wrdata=0x44332211),
|
||||
1: dict(wrdata=0x88776655),
|
||||
}
|
||||
for write_latency, sys_latency, write_delay in [(1, 0, 0), (2, 0, 1), (3, 0, 2), (4, 0, 3), (5, 1, 0)]:
|
||||
with self.subTest(write_latency=write_latency, sys_latency=sys_latency, write_delay=write_delay):
|
||||
sys_latency = [{}] * sys_latency
|
||||
write_latency_cycles = [{}] * (write_latency - 1)
|
||||
dfi_sys = [
|
||||
{7: write_ap},
|
||||
*sys_latency,
|
||||
data_clkdiv, # send with sys write_latency=1
|
||||
]
|
||||
dfi_expected = [
|
||||
*self.dfi_latency(ratio=4),
|
||||
{}, # 0
|
||||
{},
|
||||
{},
|
||||
{1: write_ap},
|
||||
# 1
|
||||
*write_latency_cycles,
|
||||
data_clk,
|
||||
{}, {}, {}, {},
|
||||
]
|
||||
self.run_test(lambda: self.Dut(
|
||||
ratio=4,
|
||||
addressbits=16,
|
||||
bankbits=3,
|
||||
nranks=1,
|
||||
databits=2*16,
|
||||
nphases=2,
|
||||
converter_kwargs=dict(write_delay=write_delay),
|
||||
), dfi_sys, dfi_expected)
|
||||
|
||||
def test_dfi_rate_converter_1_to_4_read_delayed(self):
|
||||
# When read_latency does not aligh with clkdiv boundaries, the read data must be delayed
|
||||
read = dict(cs_n=0, cas_n=0, ras_n=1, we_n=1, bank=0b111, address=0b110101)
|
||||
data_clkdiv = {
|
||||
0: dict(rddata=0x1111, rddata_valid=1), # make sure it rddata_valid on 1 phase is replicated to ratio phases
|
||||
1: dict(rddata=0x2222, rddata_valid=1),
|
||||
2: dict(rddata=0x3333, rddata_valid=1),
|
||||
3: dict(rddata=0x4444, rddata_valid=1),
|
||||
4: dict(rddata=0x5555),
|
||||
5: dict(rddata=0x6666),
|
||||
6: dict(rddata=0x7777),
|
||||
7: dict(rddata=0x8888),
|
||||
}
|
||||
data_clk = {
|
||||
0: dict(rddata=0x4444333322221111, rddata_valid=1),
|
||||
1: dict(rddata=0x8888777766665555),
|
||||
}
|
||||
for read_latency, sys_latency, read_delay in [(1, 0, 0), (2, 0, 1), (3, 0, 2), (4, 0, 3), (5, 1, 0)]:
|
||||
# read_latency is the PHY's read latency
|
||||
# sys_latency is additional latency added at sys clock
|
||||
# read_delay is from which cycle at sys4x the data is taken
|
||||
with self.subTest(read_latency=read_latency, sys_latency=sys_latency, read_delay=read_delay):
|
||||
sys_latency = [{}] * (Deserializer.LATENCY + sys_latency)
|
||||
read_latency_cycles = [{}] * (read_latency - 1)
|
||||
dfi_sys = [
|
||||
{7: read}, # 0
|
||||
{}, # 1 (read command shows up on dfi_old)
|
||||
*sys_latency,
|
||||
data_clkdiv,
|
||||
]
|
||||
dfi_expected = [ # sys2x
|
||||
*self.dfi_latency(ratio=4),
|
||||
{}, # 0
|
||||
{},
|
||||
{},
|
||||
{1: read},
|
||||
]
|
||||
dfi_input = [ # sys2x
|
||||
*self.dfi_latency(ratio=4, reset_n=False),
|
||||
{}, # 0
|
||||
{},
|
||||
{},
|
||||
{}, # read
|
||||
# 1
|
||||
*read_latency_cycles,
|
||||
data_clk,
|
||||
]
|
||||
self.run_test(lambda: self.Dut(
|
||||
ratio=4,
|
||||
addressbits=16,
|
||||
bankbits=3,
|
||||
nranks=1,
|
||||
databits=2*32,
|
||||
nphases=2,
|
||||
converter_kwargs=dict(read_delay=read_delay),
|
||||
), dfi_sys, dfi_expected, dfi_input=dfi_input)
|
||||
Loading…
Reference in New Issue