diff --git a/litedram/frontend/bridge.py b/litedram/frontend/bridge.py
index 7a20a56..2981a11 100644
--- a/litedram/frontend/bridge.py
+++ b/litedram/frontend/bridge.py
@@ -26,7 +26,6 @@ class LiteDRAMWishboneBridge(Module):
         )
         fsm.act("WRITE_DATA",
             If(port.wdata_ready,
-                port.wdata_we.eq(wishbone.sel),
                 wishbone.ack.eq(1),
                 NextState("IDLE")
             )
@@ -41,8 +40,7 @@ class LiteDRAMWishboneBridge(Module):
         # Address / Datapath
         self.comb += [
             port.adr.eq(wishbone.adr),
-            If(port.wdata_ready,
-                port.wdata.eq(wishbone.dat_w),
-            ),
+            port.wdata_we.eq(wishbone.sel),
+            port.wdata.eq(wishbone.dat_w),
             wishbone.dat_r.eq(port.rdata)
         ]
diff --git a/litedram/frontend/crossbar.py b/litedram/frontend/crossbar.py
index 729c128..8f9f98c 100644
--- a/litedram/frontend/crossbar.py
+++ b/litedram/frontend/crossbar.py
@@ -101,15 +101,17 @@ class LiteDRAMCrossbar(Module):
             self.comb += master.rdata_valid.eq(master_rdata_valid)
 
         # route data writes
-        wdata_maskselect = []
-        wdata_we_maskselect = []
-        for master in self.masters:
-            wdata_maskselect.append(master.wdata)
-            wdata_we_maskselect.append(master.wdata_we)
-        self.comb += [
-            controller.wdata.eq(reduce(or_, wdata_maskselect)),
-            controller.wdata_we.eq(reduce(or_, wdata_we_maskselect))
+        wdata_cases = {}
+        for nm, master in enumerate(self.masters):
+            wdata_cases[2**nm] = [
+                controller.wdata.eq(master.wdata),
+                controller.wdata_we.eq(master.wdata_we)
+            ]
+        wdata_cases["default"] = [
+            controller.wdata.eq(0),
+            controller.wdata_we.eq(0)
         ]
+        self.comb += Case(Cat(*master_wdata_readys), wdata_cases)
 
         # route data reads
         for master in self.masters:
diff --git a/litedram/frontend/dma.py b/litedram/frontend/dma.py
index 984cd82..e63ad10 100644
--- a/litedram/frontend/dma.py
+++ b/litedram/frontend/dma.py
@@ -72,9 +72,7 @@ class LiteDRAMDMAWriter(Module):
         ]
 
         self.comb += [
-            If(port.wdata_ready,
-                fifo.re.eq(1),
-                port.wdata_we.eq(2**(port.dw//8)-1),
-                port.wdata.eq(fifo.dout)
-            )
+            fifo.re.eq(port.wdata_ready),
+            port.wdata_we.eq(2**(port.dw//8)-1),
+            port.wdata.eq(fifo.dout)
         ]