From 8de1d91eac29407a78060cc44810f76e71162d37 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 1 Oct 2018 11:18:39 +0200 Subject: [PATCH] core: add with_bank paramteter to NativePort (cause issues on adaptation is bank is always exposed) --- litedram/common.py | 7 ++++--- litedram/frontend/crossbar.py | 24 +++++++++++++++++++++--- litedram/frontend/ecc.py | 4 ++-- 3 files changed, 27 insertions(+), 8 deletions(-) diff --git a/litedram/common.py b/litedram/common.py index 4b9d39a..597c2da 100644 --- a/litedram/common.py +++ b/litedram/common.py @@ -99,6 +99,7 @@ def cmd_description(address_width): ("addr", address_width) ] + def wdata_description(data_width, with_bank): r = [ ("data", data_width), @@ -116,7 +117,7 @@ def rdata_description(data_width, with_bank): class LiteDRAMNativePort: - def __init__(self, mode, address_width, data_width, clock_domain="sys", id=0): + def __init__(self, mode, address_width, data_width, clock_domain="sys", id=0, with_bank=False): self.mode = mode self.address_width = address_width self.data_width = data_width @@ -126,8 +127,8 @@ class LiteDRAMNativePort: self.lock = Signal() self.cmd = stream.Endpoint(cmd_description(address_width)) - self.wdata = stream.Endpoint(wdata_description(data_width, True)) - self.rdata = stream.Endpoint(rdata_description(data_width, True)) + self.wdata = stream.Endpoint(wdata_description(data_width, with_bank)) + self.rdata = stream.Endpoint(rdata_description(data_width, with_bank)) self.flush = Signal() diff --git a/litedram/frontend/crossbar.py b/litedram/frontend/crossbar.py index 2c3f4eb..7aea3cd 100644 --- a/litedram/frontend/crossbar.py +++ b/litedram/frontend/crossbar.py @@ -44,12 +44,24 @@ class LiteDRAMCrossbar(Module): data_width = self.controller.data_width # crossbar port - port = LiteDRAMNativePort(mode, self.rca_bits + self.bank_bits - self.rank_bits, self.controller.data_width, "sys", len(self.masters)) + port = LiteDRAMNativePort( + mode=mode, + address_width=self.rca_bits + self.bank_bits - self.rank_bits, + data_width=self.controller.data_width, + clock_domain="sys", + id=len(self.masters), + with_bank=self.controller.settigns.with_reordering) self.masters.append(port) # clock domain crossing if clock_domain != "sys": - new_port = LiteDRAMNativePort(mode, port.address_width, port.data_width, clock_domain, port.id) + new_port = LiteDRAMNativePort( + mode=mode, + address_width=port.address_width, + data_width=port.data_width, + clock_domain=clock_domain, + id=port.id, + with_bank=self.controller.settings.with_reordering) self.submodules += LiteDRAMNativePortCDC(new_port, port) port = new_port @@ -59,7 +71,13 @@ class LiteDRAMCrossbar(Module): addr_shift = -log2_int(data_width//self.controller.data_width) else: addr_shift = log2_int(self.controller.data_width//data_width) - new_port = LiteDRAMNativePort(mode, port.address_width + addr_shift, data_width, clock_domain, port.id) + new_port = LiteDRAMNativePort( + mode=mode, + address_width=port.address_width + addr_shift, + data_width=data_width, + clock_domain=clock_domain, + id=port.id, + with_bank=self.controller.settings.with_reordering) self.submodules += ClockDomainsRenamer(clock_domain)(LiteDRAMNativePortConverter(new_port, port, reverse)) port = new_port diff --git a/litedram/frontend/ecc.py b/litedram/frontend/ecc.py index 5037944..f7a4249 100644 --- a/litedram/frontend/ecc.py +++ b/litedram/frontend/ecc.py @@ -211,7 +211,7 @@ class LiteDRAMNativePortECC(Module, AutoCSR): ecc_wdata = BufferizeEndpoints({"source": DIR_SOURCE})(ecc_wdata) self.submodules += ecc_wdata self.comb += [ - port_from.wdata.connect(ecc_wdata.sink), + port_from.wdata.connect(ecc_wdata.sink, omit={"bank"}), ecc_wdata.source.connect(port_to.wdata) ] @@ -223,7 +223,7 @@ class LiteDRAMNativePortECC(Module, AutoCSR): self.submodules += ecc_rdata self.comb += [ ecc_rdata.enable.eq(self.enable.storage), - port_to.rdata.connect(ecc_rdata.sink), + port_to.rdata.connect(ecc_rdata.sink, omit={"bank"}), ecc_rdata.source.connect(port_from.rdata) ]