From 8ec0bc678ee0c92c14a7121f5ad6266f1e6c8709 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 6 Dec 2018 21:16:29 +0100
Subject: [PATCH] modules: improve the way we define DDR4 banks/groups

---
 litedram/modules.py | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/litedram/modules.py b/litedram/modules.py
index 8fd0cdc..d453aa2 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -343,9 +343,11 @@ class AS4C256M16D3A(SDRAMModule):
 class EDY4016A(SDRAMModule):
     memtype = "DDR4"
     # geometry
-    nbanks = 2*4 # 2 groups of 4 banks
-    nrows  = 32768
-    ncols  = 1024
+    ngroupbanks = 4
+    ngroups     = 2
+    nbanks      = ngroups * ngroupbanks
+    nrows       = 32768
+    ncols       = 1024
     # timings
     technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 4.9))
     speedgrade_timings = {
@@ -357,9 +359,11 @@ class EDY4016A(SDRAMModule):
 class MT40A1G8(SDRAMModule):
     memtype = "DDR4"
     # geometry
-    nbanks = 4*4 # 4 groups of 4 banks
-    nrows  = 65536
-    ncols  = 1024
+    ngroupbanks = 4
+    ngroups     = 4
+    nbanks      = ngroups * ngroupbanks
+    nrows       = 65536
+    ncols       = 1024
     # timings
     technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 4.9))
     speedgrade_timings = {