diff --git a/litedram/phy/ecp5ddrphy.py b/litedram/phy/ecp5ddrphy.py
index 8e10502..92c170c 100644
--- a/litedram/phy/ecp5ddrphy.py
+++ b/litedram/phy/ecp5ddrphy.py
@@ -479,5 +479,5 @@ class ECP5DDRPHY(Module, AutoCSR):
         # Write DQS Postamble/Preamble Control Path ------------------------------------------------
         # Generates DQS Preamble 1 cycle before the first write and Postamble 1 cycle after the last
         # write.
-        self.sync += dqs_preamble.eq(wrdata_en[cwl_sys_latency - 1])
-        self.sync += dqs_postamble.eq(oe_dqs)
+        self.sync += dqs_preamble.eq( wrdata_en[cwl_sys_latency:-1] == 0b10)
+        self.sync += dqs_postamble.eq(wrdata_en[cwl_sys_latency+1:] == 0b01)