From 91a9a2aeb1d98fb9c70f5b3108680a8b9902d612 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 16 Apr 2020 15:29:02 +0200 Subject: [PATCH] phy/ecp5ddrphy: fix dqs preamble/postamble control. (make it similar to 7-series/Ultrascale). --- litedram/phy/ecp5ddrphy.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litedram/phy/ecp5ddrphy.py b/litedram/phy/ecp5ddrphy.py index 8e10502..92c170c 100644 --- a/litedram/phy/ecp5ddrphy.py +++ b/litedram/phy/ecp5ddrphy.py @@ -479,5 +479,5 @@ class ECP5DDRPHY(Module, AutoCSR): # Write DQS Postamble/Preamble Control Path ------------------------------------------------ # Generates DQS Preamble 1 cycle before the first write and Postamble 1 cycle after the last # write. - self.sync += dqs_preamble.eq(wrdata_en[cwl_sys_latency - 1]) - self.sync += dqs_postamble.eq(oe_dqs) + self.sync += dqs_preamble.eq( wrdata_en[cwl_sys_latency:-1] == 0b10) + self.sync += dqs_postamble.eq(wrdata_en[cwl_sys_latency+1:] == 0b01)