From 91cae335e593ee8d828b08b5447d9a7817e37da8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?J=C4=99drzej=20Boczar?= <jboczar@antmicro.com>
Date: Fri, 23 Jul 2021 14:44:15 +0200
Subject: [PATCH] init: add parentheses around #define with an expression

---
 litedram/init.py           | 2 +-
 test/reference/ddr3_init.h | 2 +-
 test/reference/ddr4_init.h | 6 +++---
 test/reference/sdr_init.h  | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/litedram/init.py b/litedram/init.py
index 7bed74e..4916a42 100644
--- a/litedram/init.py
+++ b/litedram/init.py
@@ -707,7 +707,7 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
         r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
 
     # Define number of modules/delays/bitslips
-    r += "#define SDRAM_PHY_MODULES SDRAM_PHY_DATABITS/8\n"
+    r += "#define SDRAM_PHY_MODULES (SDRAM_PHY_DATABITS/8)\n"
     if phytype in ["USDDRPHY", "USPDDRPHY"]:
         r += "#define SDRAM_PHY_DELAYS 512\n"
         r += "#define SDRAM_PHY_BITSLIPS 8\n"
diff --git a/test/reference/ddr3_init.h b/test/reference/ddr3_init.h
index 6835acc..97e97f6 100644
--- a/test/reference/ddr3_init.h
+++ b/test/reference/ddr3_init.h
@@ -28,7 +28,7 @@
 #define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE
 #define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE
 #define SDRAM_PHY_READ_LEVELING_CAPABLE
-#define SDRAM_PHY_MODULES SDRAM_PHY_DATABITS/8
+#define SDRAM_PHY_MODULES (SDRAM_PHY_DATABITS/8)
 #define SDRAM_PHY_DELAYS 32
 #define SDRAM_PHY_BITSLIPS 8
 
diff --git a/test/reference/ddr4_init.h b/test/reference/ddr4_init.h
index a45cba5..35bad19 100644
--- a/test/reference/ddr4_init.h
+++ b/test/reference/ddr4_init.h
@@ -27,7 +27,7 @@
 #define SDRAM_PHY_WRITE_LEVELING_CAPABLE
 #define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE
 #define SDRAM_PHY_READ_LEVELING_CAPABLE
-#define SDRAM_PHY_MODULES SDRAM_PHY_DATABITS/8
+#define SDRAM_PHY_MODULES (SDRAM_PHY_DATABITS/8)
 #define SDRAM_PHY_DELAYS 512
 #define SDRAM_PHY_BITSLIPS 8
 
@@ -65,7 +65,7 @@ static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase){
         default: return 0;
         }
 }
-    
+
 static inline unsigned long sdram_dfii_pix_rddata_addr(int phase){
     switch (phase) {
         case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR;
@@ -75,7 +75,7 @@ static inline unsigned long sdram_dfii_pix_rddata_addr(int phase){
         default: return 0;
         }
 }
-    
+
 #define DDRX_MR_WRLVL_ADDRESS 1
 #define DDRX_MR_WRLVL_RESET 769
 #define DDRX_MR_WRLVL_BIT 7
diff --git a/test/reference/sdr_init.h b/test/reference/sdr_init.h
index fe8b0f1..e2be7dc 100644
--- a/test/reference/sdr_init.h
+++ b/test/reference/sdr_init.h
@@ -23,7 +23,7 @@
 #define SDRAM_PHY_CWL 2
 #define SDRAM_PHY_RDPHASE 0
 #define SDRAM_PHY_WRPHASE 0
-#define SDRAM_PHY_MODULES SDRAM_PHY_DATABITS/8
+#define SDRAM_PHY_MODULES (SDRAM_PHY_DATABITS/8)
 
 void cdelay(int i);