diff --git a/litedram/phy/model.py b/litedram/phy/model.py
index 12a45e4..15933a2 100644
--- a/litedram/phy/model.py
+++ b/litedram/phy/model.py
@@ -223,6 +223,7 @@ class DFITimingsChecker(Module):
         self.timings = new_timings
 
     def __init__(self, dfi, nbanks, nphases, timings, refresh_mode, memtype, verbose=False):
+        ref_limit = {"1x": 9, "2x": 17, "4x": 36}
         self.prepare_timings(timings, refresh_mode, memtype)
         self.add_cmds()
         self.add_rules()
@@ -297,13 +298,39 @@ class DFITimingsChecker(Module):
 
         # tREFI
         ref_ps = Signal().like(cnt)
-        ref_done = Signal()
-        self.sync += If(ref_issued != 0, ref_ps.eq(ps), ref_done.eq(1),
-            If(~ref_done, Display("[%016dps] Late refresh", ps)))
+        ref_ps_mod  = Signal().like(cnt)
+        ref_ps_diff = Signal(min=-2**63, max=2**63)
+        curr_diff   = Signal().like(ref_ps_diff)
 
-        self.sync += If((ps > (ref_ps + self.timings["tREFI"])) & ref_done & (ref_issued == 0),
+        self.comb += curr_diff.eq(ps - (ref_ps + self.timings["tREFI"]))
+        
+        # Work in 64ms periods
+        self.sync += If(ref_ps_mod < int(64e9),
+            ref_ps_mod.eq(ref_ps_mod + nphases * self.timings["tCK"])).Else(ref_ps_mod.eq(0))
+
+        # Update timestamp and difference
+        self.sync += If(ref_issued != 0, ref_ps.eq(ps), ref_ps_diff.eq(ref_ps_diff - curr_diff))
+
+        self.sync += If((ref_ps_mod == 0) & (ref_ps_diff > 0),
+            Display("[%016dps] tREFI violation (64ms period): %0d", ps, ref_ps_diff))
+
+        # Report any refresh periods longer than tREFI
+        if verbose:
+            ref_done = Signal()
+            self.sync += If(ref_issued != 0, ref_done.eq(1),
+                If(~ref_done, Display("[%016dps] Late refresh", ps)))
+
+            self.sync += If((curr_diff > 0) & ref_done & (ref_issued == 0),
                 Display("[%016dps] tREFI violation", ps), ref_done.eq(0))
 
+        # There is a maximum delay between refreshes on >=DDR
+        if memtype != "SDR":
+            refresh_mode = "1x" if refresh_mode is None else refresh_mode
+            ref_done = Signal()
+            self.sync += If(ref_issued != 0, ref_done.eq(1))
+            self.sync += If((ref_issued == 0) & ref_done & (ref_ps > (ps + ref_limit[refresh_mode] * self.timings['tREFI'])),
+                Display("[%016dps] tREFI violation (too many postponed refreshes)", ps), ref_done.eq(0))
+
 # SDRAM PHY Model ----------------------------------------------------------------------------------
 
 class SDRAMPHYModel(Module):