From 93e220741ea8e85cbb0b37835d0923fc86fad034 Mon Sep 17 00:00:00 2001 From: Piotr Binkowski Date: Fri, 14 Feb 2020 14:59:34 +0100 Subject: [PATCH 1/2] phy/model: check tREFI in 64ms time slices This modifies the verifier to by default only check if overall average tREFI length was correct in a 64ms time slice. Old method that enforces the delay between each REF command is now only used when verbose logging is enabled. --- litedram/phy/model.py | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/litedram/phy/model.py b/litedram/phy/model.py index 12a45e4..70188ba 100644 --- a/litedram/phy/model.py +++ b/litedram/phy/model.py @@ -297,11 +297,29 @@ class DFITimingsChecker(Module): # tREFI ref_ps = Signal().like(cnt) - ref_done = Signal() - self.sync += If(ref_issued != 0, ref_ps.eq(ps), ref_done.eq(1), - If(~ref_done, Display("[%016dps] Late refresh", ps))) + ref_ps_mod = Signal().like(cnt) + ref_ps_diff = Signal(min=-2**63, max=2**63) + curr_diff = Signal().like(ref_ps_diff) - self.sync += If((ps > (ref_ps + self.timings["tREFI"])) & ref_done & (ref_issued == 0), + self.comb += curr_diff.eq(ps - (ref_ps + self.timings["tREFI"])) + + # Work in 64ms periods + self.sync += If(ref_ps_mod < int(64e9), + ref_ps_mod.eq(ref_ps_mod + nphases * self.timings["tCK"])).Else(ref_ps_mod.eq(0)) + + # Update timestamp and difference + self.sync += If(ref_issued != 0, ref_ps.eq(ps), ref_ps_diff.eq(ref_ps_diff - curr_diff)) + + self.sync += If((ref_ps_mod == 0) & (ref_ps_diff > 0), + Display("[%016dps] tREFI violation (64ms period): %0d", ps, ref_ps_diff)) + + # Report any refresh periods longer than tREFI + if verbose: + ref_done = Signal() + self.sync += If(ref_issued != 0, ref_done.eq(1), + If(~ref_done, Display("[%016dps] Late refresh", ps))) + + self.sync += If((curr_diff > 0) & ref_done & (ref_issued == 0), Display("[%016dps] tREFI violation", ps), ref_done.eq(0)) # SDRAM PHY Model ---------------------------------------------------------------------------------- From 13d0350436c955e84afbcaffce640d96e68a08eb Mon Sep 17 00:00:00 2001 From: Piotr Binkowski Date: Fri, 14 Feb 2020 15:58:16 +0100 Subject: [PATCH 2/2] phy/model: add refresh postponing checks --- litedram/phy/model.py | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/litedram/phy/model.py b/litedram/phy/model.py index 70188ba..15933a2 100644 --- a/litedram/phy/model.py +++ b/litedram/phy/model.py @@ -223,6 +223,7 @@ class DFITimingsChecker(Module): self.timings = new_timings def __init__(self, dfi, nbanks, nphases, timings, refresh_mode, memtype, verbose=False): + ref_limit = {"1x": 9, "2x": 17, "4x": 36} self.prepare_timings(timings, refresh_mode, memtype) self.add_cmds() self.add_rules() @@ -322,6 +323,14 @@ class DFITimingsChecker(Module): self.sync += If((curr_diff > 0) & ref_done & (ref_issued == 0), Display("[%016dps] tREFI violation", ps), ref_done.eq(0)) + # There is a maximum delay between refreshes on >=DDR + if memtype != "SDR": + refresh_mode = "1x" if refresh_mode is None else refresh_mode + ref_done = Signal() + self.sync += If(ref_issued != 0, ref_done.eq(1)) + self.sync += If((ref_issued == 0) & ref_done & (ref_ps > (ps + ref_limit[refresh_mode] * self.timings['tREFI'])), + Display("[%016dps] tREFI violation (too many postponed refreshes)", ps), ref_done.eq(0)) + # SDRAM PHY Model ---------------------------------------------------------------------------------- class SDRAMPHYModel(Module):