From 96b273c523a89f48e4a46010bda4f1dfc4633fb3 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 6 Apr 2020 11:59:34 +0200
Subject: [PATCH] common/BitSlip: use reset_less on intermediate signal.

---
 litedram/common.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litedram/common.py b/litedram/common.py
index ba37b6a..1d5751a 100644
--- a/litedram/common.py
+++ b/litedram/common.py
@@ -93,7 +93,7 @@ class BitSlip(Module):
 
         # # #
 
-        r = Signal(2*dw)
+        r = Signal(2*dw, reset_less=True)
         self.sync += r.eq(Cat(r[dw:], self.i))
         cases = {}
         for i in range(dw):